SSL3401HN Datasheet, PDF (7/29 Pages) NXP Semiconductors – Low voltage dimmable controller for LED lighting

NXP Semiconductors
SSL3401HN
Low voltage dimmable controller for LED lighting
If V_DD is below the POR rising edge threshold voltage, the SSL3401HN remains in Reset
mode. Otherwise, the IC enters the Active mode.
During the Reset mode, all interface pins are configured as input with a weak pull-up
current. External pull-down resistors are required for those pins which must be LOW
during this phase.
8.2.2 Active mode
Active mode is the normal operating mode when V_DD exceeds the POR rising edge
threshold voltage and pin RESET is set HIGH or left open.
After leaving Reset mode, an initialization phase occurs. This phase consists of:
• The calibration of the internal DAC and ADC converters based on the internal
reference voltage
• The reading of parameter external parameter settings (if available)
• The detection of the comparator external common-mode offset
• The calculation of parameter values required for IC operation
The application power supply type detection (AC or DC) and the supply frequency (50 Hz
or 60 Hz) detection are executed.
The boost driver outputs BSTDRVA and BSTDRVB are active only after the DAC
calibration and the comparator common-mode offset detection are completed.
After the initialization phase, the feedback loops are active and all protection circuits are
on and continuously monitoring for abnormal events.
8.3 Power MOSFET control
The SSL3401HN is designed for use with an external inverting MOSFET driver.
Depending on the input impedance of the external driver, a single output or double outputs
can be used from the SSL3401HN.
8.4 Input current control
The input current is controlled by setting a voltage at the comparator negative input. The
positive input is connected to the coil current sensing resistor R_ICBST. A V_DD referred level
shifter is inserted between R_ICBST and the positive input of the comparator. It consists of
resistors with the same nominal value. The SSL3401HN detects and compensates
automatically for the level shifter offset as well as for gain because of variation in the
resistance value.
Optionally, an input latching current can be created to improve compatibility with
leading-edge dimmers.
The average input current, with the latching current set to zero, is set to 1.1 A with a
200 m R_ICBST. This setting is adequate for a 7.5 W input power system. With a different
input power level, the R_ICBST value must be scaled proportionally to get an optimum
start-up behavior and dimming sensitivity range. The equivalent R_ICBST value can be
calculated with Equation 1:
SSL3401HN
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 28 January 2014
© NXP B.V. 2014. All rights reserved.
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