SA571 Datasheet, PDF (7/11 Pages) NXP Semiconductors – Compandor

Philips Semiconductors
Compandor
Product specification
SA571
INPUT = 0dBm
0
–20dBm
3
–40dBm
10k
1MEG
FREQUENCY (Hz)
SR00686
Figure 12. Rectifier Frequency Response vs Input Level
VARIABLE GAIN CELL
Figure 13 is a diagram of the variable gain cell. This is a linearized
two-quadrant transconductance multiplier. Q₁, Q₂ and the op amp
provide a predistorted drive signal for the gain control pair, Q₃ and
Q₄. The gain is controlled by I_G and a current mirror provides the
output current.
The op amp maintains the base and collector of Q₁ at ground
potential (V_REF) by controlling the base of Q₂. The input current I_IN
(=V_IN/R₂) is thus forced to flow through Q₁ along with the current I₁,
so I_C1=I₁+I_IN. Since I₂ has been set at twice the value of I₁, the
current through Q₂ is:
I₂-(I₁+I_IN)=I₁-I_IN=I_C2.
The op amp has thus forced a linear current swing between Q₁ and
Q₂ by providing the proper drive to the base of Q₂. This drive signal
will be linear for small signals, but very non-linear for large signals,
since it is compensating for the non-linearity of the differential pair,
Q₁ and Q₂, under large signal conditions.
V+
I₁
140µA
R₂
20k
Q₁
Q₂
V_IN
I_IN
Q₃
Q₄
I₂ (= 2I₁)
I_G
280µA
NOTE:
IG
IG VIN
V–
IOUT + _I1 IIN + _{I2 R2}
Figure 13. Simplified ∆G Cell Schematic
SR00687
The key to the circuit is that this same predistorted drive signal is
applied to the gain control pair, Q₃ and Q₄. When two differential
pairs of transistors have the same signal applied, their collector
current ratios will be identical regardless of the magnitude of the
currents. This gives us:
I_C1
I_C2
+
I_C4
I_C3
+
I₁ ) I_IN
I₁ * I_IN
plus the relationships I_G=I_C3+I_C4 and I_OUT=I_C4-I_C3 will yield the
multiplier transfer function,
I_OUT
+
I_G
I₁
I_IN
+
V_IN I_G
R₂ I₁
This equation is linear and temperature-insensitive, but it assumes
ideal transistors.
4
V_OS = 5mV
3
4mV
2
3mV
2mV
1
1mV
.34
–6
0
+6
INPUT LEVEL (dBm)
SR00688
Figure 14. ∆G Cell Distortion vs Offset Voltage
If the transistors are not perfectly matched, a parabolic, non-linearity
is generated, which results in second harmonic distortion. Figure 14
gives an indication of the magnitude of the distortion caused by a
given input level and offset voltage. The distortion is linearly
proportional to the magnitude of the offset and the input level.
Saturation of the gain cell occurs at a +8dBm level. At a nominal
operating level of 0dBm, a 1mV offset will yield 0.34% of second
harmonic distortion. Most circuits are somewhat better than this,
which means our overall offsets are typically about mV. The
distortion is not affected by the magnitude of the gain control
current, and it does not increase as the gain is changed. This
second harmonic distortion could be eliminated by making perfect
transistors, but since that would be difficult, we have had to resort to
other methods. A trim pin has been provided to allow trimming of the
internal offsets to zero, which effectively eliminated
second harmonic distortion. Figure 15 shows the simple trim
network required.
Figure 16 shows the noise performance of the ∆G cell. The
maximum output level before clipping occurs in the gain cell is
plotted along with the output noise in a 20kHz bandwidth. Note that
the noise drops as the gain is reduced for the first 20dB of gain
reduction. At high gains, the signal to noise ratio is 90dB, and the
total dynamic range from maximum signal to minimum noise is
110dB.
V_CC
6.2k
To THD Trim
≈200pF
R
3.6V
20k
Figure 15. THD Trim Network
SR00689
1997 Aug 14
7