SA571 Datasheet, PDF (6/11 Pages) NXP Semiconductors – Compandor

Philips Semiconductors
Compandor
Product specification
SA571
R₂
∆G
R₁
C_IN
V_IN
R_DC^*
C_RECT^*
R_DC^*
C_F^*
R₃
C_DC^*
V_OUT
R₄ VREF
ǒ Ǔ ^NOTES:
GAIN +
1
R1 R2 IB ²
2R3 VINavg
I_B = 140µA
External components
Figure 8. Basic Compressor
I = V_IN / R₁
V+
R₁
V_IN
R_S
10k
C_R
I_G
SR00682
Figure 9. Rectifier Concept
SR00684
CIRCUIT DETAILS—RECTIFIER
Figure 9 shows the concept behind the full-wave averaging rectifier.
The input current to the summing node of the op amp, V_INR₁, is
supplied by the output of the op amp. If we can mirror the op amp
output current into a unipolar current, we will have an ideal rectifier.
The output current is averaged by R₅, CR, which set the averaging
time constant, and then mirrored with a gain of 2 to become I_G, the
gain control current.
Figure 10 shows the rectifier circuit in more detail. The op amp is a
one-stage op amp, biased so that only one output device is on at a
time. The non-inverting input, (the base of Q₁), which is shown
grounded, is actually tied to the internal 1.8V V_REF. The inverting
input is tied to the op amp output, (the emitters of Q₅ and Q₆), and
the input summing resistor R₁. The single diode between the bases
of Q₅ and Q₆ assures that only one device is on at a time. To detect
the output current of the op amp, we simply use the collector
currents of the output devices Q₅ and Q₆. Q₆ will conduct when the
input swings positive and Q₅ conducts when the input swings
negative. The collector currents will be in error by the a of Q₅ or Q₆
on negative or positive signal swings, respectively. ICs such as this
have typical NPN βs of 200 and PNP βs of 40. The a’s of 0.995 and
0.975 will produce errors of 0.5% on negative swings and 2.5% on
positive swings. The 1.5% average of these errors yields a mere
0.13dB gain error.
At very low input signal levels the bias current of Q₂, (typically
50nA), will become significant as it must be supplied by Q₅. Another
low level error can be caused by DC coupling into the rectifier. If an
offset voltage exists between the V_IN input pin and the base of Q₂,
an error current of V_OS/R₁ will be generated. A mere 1mV of offset
will cause an input current of 100nA which will produce twice the
error of the input bias current. For highest accuracy, the rectifier
should be coupled into capacitively. At high input levels the β of the
PNP Q₆ will begin to suffer, and there will be an increasing error until
the circuit saturates. Saturation can be avoided by limiting the
current into the rectifier input to 250µA. If necessary, an external
resistor may be placed in series with R₁ to limit the current to this
value. Figure 11 shows the rectifier accuracy vs input level at a
frequency of 1kHz.
V+
Q₃
Q₇
Q₁ Q₂
Q₄
D₁
I₁
I₂
Q₅
Q₆
R₁
10k
V_IN
R_S
10k
Q₈
Q₉
C_R
V–
NOTE:
VIN avg
IG + 2 _{R 1}
Figure 10. Simplified Rectifier Schematic
SR00683
At very high frequencies, the response of the rectifier will fall off. The
roll-off will be more pronounced at lower input levels due to the
increasing amount of gain required to switch between Q₅ or Q₆
conducting. The rectifier frequency response for input levels of
0dBm, -20dBm, and -40dBm is shown in Figure 12. The response at
all three levels is flat to well above the audio range.
+1
0
–1
–40
–20
0
RECTIFIER INPUT dBm
Figure 11. Rectifier Accuracy
SR00685
1997 Aug 14
6