SA56614-XX Datasheet, PDF (7/14 Pages) NXP Semiconductors – CMOS system reset

Philips Semiconductors
CMOS system reset
Product data
SA56614-XX
TECHNICAL DESCRIPTION
The SA56614-XX is a CMOS device designed to monitor the
system’s power source and provide a system reset function in the
event the supply voltage sags below an acceptable level for the
system to reliably operate. The SA56614 generates a compatible
reset signal for a wide variety of microprocessor and logic systems.
The device can operate at voltages up to 12 volts. The series
includes several versions providing precision threshold voltage reset
values of 2.0, 2.7, 2.8, 2.9, 3.0, 3.1, 4.2, 4.6, and 4.7 V. The reset
threshold incorporates a typical hysteresis of (V_S × 0.05) volts to
prevent erratic resets from being generated. The SA56614 operates
at very low supply currents, typically 0.25 µA, while offering a high
precision of threshold detection (±2%).
The output of the SA56614 incorporates an active Totem-Pole
output topology comprised of complimentary P-Channel and
N-Channel FETs. A P-Channel FET is on the high supply side and
when ON pulls the output to or near the V_DD supply voltage from
which output source current can be obtained. A complimentary
N-Channel FET is on the low or ground side, and actively pulls the
output LOW or to ground with the capability of sinking current into
the output. Both devices supply system reset signals. The user
should keep in mind, when connecting the SA56614 to a system, the
effect of supplying source current from the output of the SA56614 on
the system. This is of particular importance where the SA56614 is
operated from a different supply source than the rest of the system.
Figure 12 is a functional block diagram of the SA56614. The internal
reference source voltage (V_REF) is typically 0.8 V over the operating
temperature range. The reference voltage is connected to the
non-inverting input of the threshold comparator while the inverting
input monitors the supply voltage through a resistor divider network
made up of R₁, R₂, and R₃. The output of the threshold comparator
drives the totem-pole output stage of the device.
When the supply voltage sags to the threshold detection voltage, the
resistor divider network supplies a voltage to the inverting input of
the threshold comparator which is less than that of V_REF, causing
the output of the comparator to adopt a HIGH output state. This
causes the high side P-Channel FET of the Totem-Pole output stage
to turn OFF while simultaneously turning the low side N-Channel
FET from OFF to an active ON state, pulling the output to a LOW
voltage state. The device adheres to a true input/output logic
protocol. The output goes to a LOW voltage state when input is
LOW (below V_S) and the output HIGH goes to a HIGH voltage state
when the input is HIGH (above V_S).
The low side N-Channel FET (TR₃) establishes threshold hysteresis
by turning ON whenever the threshold comparator’s output goes to
a HIGH state (when V_DD sags to or below the threshold level). TR₃’s
turning ON causes additional current to flow through resistors R₁,
and R₂ causing the inverting input of the threshold comparator to be
pulled even lower. For the comparator to reverse its output polarity
and turn OFF TR₃, the V_DD source voltage must overcome this
additional pull-down voltage present on the comparator’s inverting
input. The differential voltage required to do this establishes the
hysteresis voltage of the sensed threshold voltage. Typically it is
(V_S × 0.05) volts.
When the V_DD voltage sags and is at or below the Detection
Threshold (V_SL), the device will assert a Reset LOW output at or
very near ground potential. As the V_DD voltage rises from
(V_DD < V_SL) to V_SH or higher, the reset is released and the output
follows V_DD. Conversely, decreases in V_DD from (V_DD > V_SL) to V_SL
or lower cause the output to be pulled to ground.
Hysteresis Voltage = Release Voltage – Detection Threshold Voltage
V_HYS = V_SH – V_SL
where:
V_SH = V_SL + V_HYS ≅ V_REF(R₁ + R₂) / R₂
V_SL = V_REF(R₁ + R₂ + R₃) / (R₂ + R₃)
When V_DD drops below the minimum operating voltage, typically
less than 0.95 volts, the output is undefined and output reset low
assertion is not guaranteed. At this level of V_DD the output will try to
rise to V_DD.
The V_REF voltage is typically 0.8 V. The devices are fabricated using
a high resistance CMOS process and utilize high resistance R₁, R₂,
and R₃ values requiring very small amounts of current. This
combination achieves very efficient low power performance over the
full operating temperature.
V_DD
2
V_REF
R
NE56614-XX
R₁
R₂
TR₁
V_OUT
1
TR₂
V_SS
3
R₃
TR₃
Figure 12. Functional diagram
SL01353
2001 Jun 19
7