BUK110-50GL Datasheet, PDF (7/11 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK110-50GL
Energy & Time
1.5
1.0
Energy / J
BUK110-50GL
Time / ms
0.5
Tj(TO)
0
-60
-20
20
60
100 140 180 220
Tmb / C
Fig.14. Typical overload protection characteristics.
Conditions: V_DD = 13 V; V_IS = 5 V; SC load = 30 mΩ
ID / A
50
BUK110-50GL
40
30
typ.
20
10
0
50
60
70
VDS / V
Fig.15. Typical clamping characteristics, 25 ˚C.
I_D = f(V_DS); conditions: V_IS = 0 V; t_p ≤ 50 µs
VIS(TO) / V
2
1
max.
typ.
min.
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.16. Input threshold voltage.
V_IS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = 5 V
IIS / uA
500
BUK110-50GL
400
300
200
100
0
0
Fig.17.
2
4
6
8
VIS / V
Typical DC input characteristics, T_j = 25 ˚C.
I_IS = f(V_IS); normal operation
IIS / mA
5
4
3
PROTECTION LATCHED
RESET
BUK110-50GL
2
1
NORMAL
0
0
2
4
6
8
VIS / V
Fig.18. Typical DC input characteristics, T_j = 25 ˚C.
I_ISL = f(V_IS); overload protection operated ⇒ I_D = 0 A
IS / A
200
BUK110-50GL
150
100
50
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VSD / V
Fig.19. Typical reverse diode current, T_j = 25 ˚C.
I_S = f(V_SDS); conditions: V_IS = 0 V; t_p = 250 µs
June 1996
7
Rev 1.000