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BUK110-50GL Datasheet, PDF (5/11 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET
Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK110-50GL
120 PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.2. Normalised limiting power dissipation.
PD% = 100⋅PD/PD(25 ˚C) = f(Tmb)
ID%
120
Normalised Current Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.3. Normalised continuous drain current.
ID% = 100⋅ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V
ID & IDM / A
1000
BUK110-50GL
Overload protection characteristics not shown
100
RDS(ON) = VDS/ID
tp =
10 us
100 us
10
DC
1 ms
10 ms
100 ms
1
1
10
100
VDS / V
Fig.4. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Zth / (K/W)
10
BUK110-50GL
1 D=
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0
PD
tp
D
=
tp
T
0.001
1E-07
1E-05
1E-03
t/s
T
t
1E-01
Fig.5. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
1E+01
ID / A
120
BUK110-50GL
110
VIS / V =
100
90
6.0
80
5.5
70
5.0
60
4.5
50
4.0
40
30
3.5
20
3.0
10
2.5
0
0 2 4 6 8 10 12 14 16 18 20
VDS / V
Fig.6. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 250 µs & tp < td sc
ID / A
100
BUK110-50GL
90
VIS / V =
80
5.0
70
4.5
60
50
4.0
40
3.5
30
20
3.0
10
2.5
0
0
1
2
3
4
5
VDS / V
Fig.7. Typical on-state characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 250 µs
June 1996
5
Rev 1.000