74HCHCT377 Datasheet, PDF (7/7 Pages) NXP Semiconductors – Octal D-type flip-flop with data enable; positive-edge trigger

Philips Semiconductors
Octal D-type flip-flop with data enable;
positive-edge trigger
AC WAVEFORMS
Product specification
74HC/HCT377
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.6 Waveforms showing the clock (CP) to output (Q_n) propagation delays, the clock pulse width, output
transition times and the maximum clock pulse frequency.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.7 Waveforms showing the data set-up and hold times from the data input (D_n) and from the data enable input
(E) to the clock (CP).
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
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