74HCHCT377 Datasheet, PDF (2/7 Pages) NXP Semiconductors – Octal D-type flip-flop with data enable; positive-edge trigger

Philips Semiconductors
Octal D-type flip-flop with data enable;
positive-edge trigger
Product specification
74HC/HCT377
FEATURES
• Ideal for addressable register applications
• Data enable for address and data synchronization
applications
• Eight positive-edge triggered D-type flip-flops
• See “273” for master reset version
• See “373” for transparent latch version
• See “374” for 3-state version
• Output capability: standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT377 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT377 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. A common
clock (CP) input loads all flip-flops simultaneously when
the data enable (E) is LOW. The state of each D input, one
set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Q_n) of the flip-flop.
The E input must be stable only one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
CONDITIONS
t_PHL/ t_PLH
f_max
C_I
C_PD
propagation delay CP to Q_n
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
TYPICAL
UNIT
HC HCT
13 14 ns
77 53 MHz
3.5 3.5 pF
20 20 pF
December 1990
2