74HC652 Datasheet, PDF (7/10 Pages) NXP Semiconductors – Octal bus transceiver/register; 3-state

Philips Semiconductors
Octal bus transceiver/register; 3-state
Product specification
74HC/HCT652
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
I_CC category: MSI.
Note to the HCT types
The value of additional quiescent supply current (∆I_CC) for unit a load of 1 is given in the family specifications.
To determine ∆I_CC per input, multiply this value by the unit load coefficient shown in the table below
INPUT
UNIT LOAD COEFFICIENT
S_AB, S_BA
A₀ to A₇ and B₀ to B₇
CP_AB, CP_BA
OE_AB
OE_BA
0.75
0.75
1.50
1.50
1.50
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF.
T_amb (°C)
TEST CONDITIONS
INPUT PARAMETER
MIN.
+25
TYP.
MAX.
−40 to +85
MIN. MAX.
−40 to +125
MIN. MAX.
UNIT
V_CC
(V)
WAVEFORMS
t_PHL/t_PLH propagation delay
−
A_n, B_n to B_n, A_n
t_PHL/t_PLH propagation delay
−
CP_AB, CP_BA to B_n, A_n
t_PHL/t_PLH propagation delay
−
S_AB, S_BA to B_n, A_n
t_PZH/t_PZL 3-state output enable
−
time
OE_AB, OE_BA to A_n, B_n
t_PHZ/t_PLZ 3-state output disable −
time
OE_AB, OE_BA to A_n, B_n
t_THL/t_TLH output transition time
−
16 27 − 34 −
23 39 − 49 −
27 46 − 55 −
18 33 − 41 −
16 35 − 44 −
5 12 − 15 −
41 ns 4.5 Fig.6
59 ns 4.5 Fig.7
66 ns 4.5 Fig.8
50 ns 4.5 Fig.9
53 ns 4.5 Fig.9
18 ns 4.5 Fig.6, 8
t_W
clock pulse width
16 6 −
20 −
24 −
ns 4.5 Fig.7
HIGH or LOW
CP_AB or CP_BA
t_su
set-up time
10 5 −
13 −
15 −
ns 4.5 Fig.7
A_n, B_n to CP_AB, CP_BA
t_h
hold time
5 −2 −
6−
8
−
ns 4.5 Fig.7
A_n, B_n to CP_AB, CP_BA
f_max
maximum clock pulse 30 83 −
24 −
20 −
MHz 4.5 Fig.7
frequency
September 1993
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