74HC652 Datasheet, PDF (2/10 Pages) NXP Semiconductors – Octal bus transceiver/register; 3-state

Philips Semiconductors
Octal bus transceiver/register; 3-state
Product specification
74HC/HCT652
FEATURES
• Multiplexed real-time and stored
data
• Independent register for A and B
buses
• Independent enables for A and B
buses
• 3-state
• Output capability: Bus driver
• Low power consumption by CMOS
technology
• I_CC category: MSI.
APPLICATIONS
• Bus interfaces.
DESCRIPTION
The 74HC/HCT652 are high-speed
SI-gate CMOS devices and are pin
compatible with Low power Schottky
TTL (LSTTL). They are specified in
compliance with Jedec standard
no. 7A.
The 74HC/HCT652 consist of 8
non-inverting bus transceiver circuits
with 3-state outputs, D-type flip-flops
and central circuitry arranged for
multiplexed transmission of data
directly from the data bus or from the
internal storage registers. Data on the
“A” or “B” or both buses, will be stored
in the internal registers, at the
appropriate clock pins (CP_AB or
CP_BA) regardless of the select pins
(S_AB and S_BA) or output enable (OE_AB
and OE_BA) control pins. Depending
on the select inputs S_AB and S_BA data
can directly go from input to output
(real time mode) or data can be
controlled by the clock (storage
mode), this is when the output enable
pins this operating mode permits. The
output enable pins OE_AB and OE_BA
determine the operation mode of the
transceiver. When OE_AB is LOW, no
data transmission from A_n to B_n is
possible and when OE_BA is HIGH,
there is no data transmission from B_n
to A_n possible. When S_AB and S_BA are
in the real time transfer mode, it is
also possible to store data without
using the internal D-type flip-flops by
simultaneously enabling OE_AB and
OE_BA. In this configuration each
output reinforces its input. Thus when
all other data sources to the two sets
of bus lines are at high-impedance,
each set of the bus lines will remain at
its last state. This type differs from the
HC/HCT646 in one extra
bus-management function. This is the
possibility to transfer stored “A data to
the “B” bus and transfer stored ”B”
data to the ”A” bus at the same time.
The examples at the application
information demonstrate all bus
management functions.
Schmitt-trigger action in the clock
inputs makes the circuit highly
tolerant to slower clock rise and fall
times.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25°C; t_r = t_f = 6 ns; V_CC = 4.5 V; C_L = 50 pF.
SYMBOL PARAMETER
CONDITIONS
t_PLH/t_PZL
t_PHZ/t_PZL
t_PHZ/t_PLZ
f_max
C_I
C_PD
propagation delay A_n/B_n to B_n /A_n
propagation delay CP_AB/CP_BA to B_n /A_n
propagation delay S_AB/S_BA to B_n /A_n
3-state output enable time OE_AB/OE_BA to B_n/A_n
3-state output disable time OE_AB/OE_BA to B_n/A_n
maximum clock frequency
input capacitance
power dissipation capacitance per channel
C_L = 15 pF;
V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz; C_L = output load capacitance in pF;
f_o = output frequency in MHz; V_CC = supply voltage in V;
∑ (C_L × V_CC2 × f_o) = sum of the outputs
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
September 1993
2
TYPICAL
HC HCT
13
13
18
20
20
23
14
15
12
13
92
92
3.5 3.5
26
28
UNIT
ns
ns
ns
ns
ns
MHz
pF
pF