74HC4518 Datasheet, PDF (7/7 Pages) NXP Semiconductors – Dual synchronous BCD counter

Philips Semiconductors
Dual synchronous BCD counter
AC WAVEFORMS
Product specification
74HC/HCT4518
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.7 Waveforms showing hold and set-up times for nCP₀ to nCP₁ and nCP₁ to nCP₀.
Conditions:
nCP₁ = HIGH while nCP₀ is triggered on a
LOW-to-HIGH transition and nCP₀ = LOW,
while nCP₁ is triggered on a HIGH-to-LOW transition.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.8 Waveforms showing the minimum pulse widths for nCP₀, nCP₁ and nMR inputs; the removal time for nMR
and the propagation delay for nMR to nQ_n outputs and the maximum clock pulse frequency.
Conditions:
nCP₁ = HIGH while nCP₀ is triggered on a
LOW-to-HIGH transition and nCP₀ = LOW,
while nCP₁ is triggered on a HIGH-to-LOW transition.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.9 Waveforms showing the propagation delays for nCP₀, nCP₁ to nQ_n outputs and the output transition times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
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