74HC4518 Datasheet, PDF (2/7 Pages) NXP Semiconductors – Dual synchronous BCD counter

Philips Semiconductors
Dual synchronous BCD counter
Product specification
74HC/HCT4518
FEATURES
• Output capability: standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4518 are high-speed Si-gate CMOS
devices and are pin compatible with the “4518” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4518 are dual 4-bit internally synchronous
BCD counters with an active HIGH clock input (nCP₀) and
an active LOW clock input (nCP₁), buffered outputs from
all four bit positions (nQ₀ to nQ₃) and an active HIGH
overriding asynchronous master reset input (nMR).
The counter advances on either the LOW-to-HIGH
transition of nCP₀ if nCP₁ is HIGH or the HIGH-to-LOW
transition of nCP₁ if nCP₀ is LOW. Either nCP₀ or nCP₁
may be used as the clock input to the counter and the other
clock input may be used as a clock enable input. A HIGH
on nMR resets the counter (nQ₀ to nQ₃ = LOW)
independent of nCP₀ and nCP₁.
APPLICATIONS
• Multistage synchronous counting
• Multistage asynchronous counting
• Frequency dividers
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL PARAMETER
CONDITIONS
TYPICAL
HC
HCT
t_PHL/ t_PLH propagation delay nCP₀, nCP₁ to nQ_n
C_L = 15 pF; V_CC = 5 V 20
24
t_PHL
propagation delay nMR to nQ_n
13
14
f_max
maximum clock frequency
61
55
C_I
input capacitance
3.5
3.5
C_PD
power dissipation capacitance per counter notes 1 and 2
29
27
UNIT
ns
ns
MHz
pF
pF
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2