74HC162 Datasheet, PDF (7/11 Pages) NXP Semiconductors – Presettable synchronous BCD decade counter; synchronous reset

Philips Semiconductors
Presettable synchronous BCD decade
counter; synchronous reset
Product specification
74HC/HCT162
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I_CC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF
T_amb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
+25
min. typ. max.
74HC
−40 to +85
min. max.
−40 to +125
min. max.
UNIT
V_CC ^WAVEFORMS
(V)
t_PHL/ t_PLH propagation delay
58 190
240
285 ns
2.0 Fig.8
CP to Q_n
21 38
48
57
4.5
17 32
41
48
6.0
t_PHL/ t_PLH propagation delay
69 215
270
325 ns
2.0 Fig.8
CP to TC
25 43
54
65
4.5
20 37
46
55
6.0
t_PHL/ t_PLH propagation delay
39 150
190
225 ns
2.0 Fig.9
CET to TC
14 30
38
45
4.5
11 26
33
38
6.0
t_THL/ t_TLH output transition
time
t_W
clock pulse width
HIGH or LOW
19 75
7 15
6 13
80 22
16 8
14 6
95
19
16
100
20
17
110 ns
22
19
120
ns
24
20
2.0 Figs 8 and 9
4.5
6.0
2.0 Fig.8
4.5
6.0
t_su
set-up time
100 28
MR, D_n to CP
20 10
17 8
125
150
ns
2.0 Figs 9 and 11
25
30
4.5
21
26
6.0
t_su
set-up time
PE to CP
135 39
27 14
23 11
170
205
ns
2.0 Fig.9
34
41
4.5
29
35
6.0
t_su
set-up time
200 69
CEP, CET to CP 40 25
34 20
250
300
ns
2.0 Fig.12
50
60
4.5
43
51
6.0
t_h
hold time
0 −17
0
0
ns
2.0 Figs 9, 11 and
D_n, PE, CEP,
0 −6
0
0
4.5 12
CET, MR to CP 0 −5
0
0
6.0
f_max
maximum clock
6.0 19
pulse
30 57
frequency
35 68
4.8
4.0
MHz 2.0 Fig.8
24
20
4.5
28
24
6.0
December 1990
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