P83CL882 Datasheet, PDF (60/88 Pages) NXP Semiconductors – 80C51 Ultra Low Power ULP telephony controller

Philips Semiconductors
80C51 Ultra Low Power (ULP) telephony controller
Product specification
P83CL882
6.9.5 DATA TRANSMISSION
Data transmission is enabled if bit MTEN in register MCON
is set to a logic 1. If MTEN is a logic 0, data transmission
is disabled and MOUT[2:0] is set to ‘111’ to zero the
currents in the resistive DAC. Setting MTEN to a logic 1
sets MOUT[2:0] to the idle value ‘100’. This results in
a value close to ¹/₂V_DD on the output signal of the external
DAC. Transmission is started by loading the first byte into
register MBUF. All bytes are transmitted starting with the
MSB.
A message is transferred in a block of 3 or more bytes, the
first two bytes being the programmed Manchester
preamble pattern. In order to insert the preamble pattern,
the first two bytes AAH and AxH (with ‘x’ being the
MPR3 to MPR0 value programmed in the receiver MSK
modem) have to be written to MBUF by software.
After this, the first byte of the message is written to MBUF.
As soon as MBUF is ready to accept new input, signal MTI
is set.
The minimum time between two MTI interrupts is:
t_min = _{b----a---u----d-8----r--a---t--e-}
If no new byte is written to MBUF at the end of a byte
transmission, the modem transmitter stops transmission
and MOUT[2:0] is set to the idle state ‘100’.
MTI must be cleared explicitly. If MTEN is reset during
transmission, the transmitter will finish the transmission of
the current byte and then will set MOUT[2:0] to the off
state ‘111’. No interrupt on MTI will be generated at the
end of the transmission.
handbook, full pagewidth
write write
set MBUF MBUF
MTEN AAH ADH
80C51
access
write
MBUF
AAH
write
MBUF
55H
write
MBUF
55H
clear
MTI
MOUT
data AAH data ADH data AAH data 55H
data 55H
MTI
TX_MUTE
MGK229
Fig.28 Data transmission timing diagram.
2001 Jun 19
60