P83CL882 Datasheet, PDF (10/88 Pages) NXP Semiconductors – 80C51 Ultra Low Power ULP telephony controller

Philips Semiconductors
80C51 Ultra Low Power (ULP) telephony controller
Product specification
P83CL882
6.1.3 ON-CHIP CLOCKS
The microcontroller does not need a clock signal to run
instructions, because the CPU is built using the Philips
exclusive handshake technology. The peripheral blocks
however are connected to a clock for synchronization with
the outside world (e.g. MSK) or for a timed application (e.g.
Timer 2). The block related SFRs (peripheral function) are
therefore updated/modified with the applied clock. Two
prescalers (PSC1 and PSC2) are implemented which
allow the generation of two programmable clock signals
f_psc and f_per for internal usage.
Signal f_psc from PSC1 is the default input clock of the timer
blocks. The complete timer functionality is specified in the
Section 6.5. Connected timers are the three 16-bit
timers Timer 0, 1 and 2 and the 8-bit Watchdog Timer.
The time interval of the connected timers can be adjusted
by programming of PSC1. The output frequency f_psc can
be changed by selecting the division factor with the bits
PRESC.[2:0], (see Table 7).
All peripheral blocks, which require a clock signal: MSK,
and I²C-bus interface are connected to the clock signal
f_per. PSC2 can be programmed by setting bits PRESC.4
and PRESC.3 (see Table 7). The choice of the division
factor must guarantee that all of the peripheral blocks are
within their specification, specially if an external clock
source of up to 12 MHz is applied.
Additionally Timer 1 and Timer 0 have a multiplexer on the
clock input to choose from 4 different clock sources.
The multiplexers are switched by setting user controllable
bits in the SYSCON SFR (bits 7 to 4). In the default setting
both timers are incrementing on the clock signal f_psc
coming from PSC1. Timer 1 and Timer 0 can however also
run on clock signal f_per coming from PSC2. If used in the
proper way this flexibility on the timer input sources can
substantially contribute to a decrease in power
consumption. Ideas and tips to reduce power consumption
are given in Chapter 9.
The clock source of Timer 1 and Timer 0 can also be
switched to an external clock input signal T1 or T0 which
are multiplexed with one of the device input pins.
This mode is also functional even when there is no system
clock available. This means when a clock source is
supplied on a port pin Timer 1 or Timer 0 can count and
generate interrupts even when the chip is in Power-down
mode. More details are specified in Section 6.5.
The last multiplexer input to Timer 1 and Timer 0 is an
auxiliary mode which can be used to obtain the operation
speed from the handshake CPU. If this mode is activated
for the Timer 1 input source, the timer increments on every
ROM request. This means the timer increments by three
for a three byte instruction and by two for a two byte
instruction etc. If the auxiliary mode is activated for Timer 0
the timer increments on every instruction executed by
the CPU. This means the timer register holds the number
of instructions executed in a certain time frame. More
ideas and tips on how these clock source modes can be
used together with the handshake CPU can be found in
Chapter 9.
Table 3 Timer 1 input source select modes
Bits T1SRC[1:0] are defined in SYSCON SFR.
T1SRC1 T1SRC0
DESCRIPTION
0
0
f_psc is the Timer 1 clock input
0
1 T1 is the Timer 1 clock input
1
0 the ROMreq signal is the Timer 1
clock input
1
1
f_per is the Timer 1 clock input
Table 4 Timer 0 input source select modes
Bits T0SRC[1:0] are defined in SYSCON SFR.
T0SRC1 T0SRC0
DESCRIPTION
0
0
f_psc is the Timer 0 clock input
0
1 T0 is the Timer 0 clock input
1
0 the InstrReq signal is the Timer 0
clock input
1
1
f_per is the Timer 0 clock input
2001 Jun 19
10