TDA4884 Datasheet, PDF (6/28 Pages) NXP Semiconductors – Advanced monitor video controller for OSD

Philips Semiconductors
Three gain control video pre-amplifier for OSD
Product specification
TDA4884
to be faster than 75 ns/V during transition from
1 to 3.5 V.
7.4 Vertical blanking
The vertical blanking pulse will be detected if the input
voltage (pin 10) is higher than the threshold voltage for
approximately 320 ns but does not exceed the threshold
for the clamping pulse in the time between. During the
vertical blanking pulse the input clamping is disabled to
avoid misclamping in the event of composite input signals.
The input signal is blanked and the artificial black level is
inserted instead, thus the output signal is at reference
black level. The DC value of the reference black level will
be adjusted by cut-off stabilization (see below).
7.5 Horizontal blanking
During horizontal blanking (pin 9) the output signal is set to
reference black level and output clamping is activated. If
the voltage at pin 9 exceeds the switch-off threshold, the
signal is blanked and switched to ultra-black level for
screen protection and spot suppression during V-flyback.
Ultra-black level is the lowest possible output voltage (at
voltage outputs) and is not dependent on cut-off
stabilization.
7.6 Cut-off and black-level stabilization
For cut-off stabilization (DC coupling to the CRT) and
black-level stabilization (AC coupling) the video signal at
the cathode or the coupling capacitor is divided by an
adjustable voltage divider and fed to the feedback inputs
(pins 18, 15 and 12). During horizontal blanking time this
signal is compared with an internal DC voltage of
approximately 5.8 V. Any difference will lead to a
reference black-level correction by charging or discharging
the integrated capacitor which stores the reference
black-level information between the horizontal blanking
pulses.
7.7 On screen display
For OSD fast switching of control pin 6 to less than 1 V
(e.g. 0.7 V) blanks the input signals. The OSD signals can
easily be inserted to the external cascode transistor
(see Fig.3).
7.8 Test mode
During test mode (pins 9 and 10 connected to V_P) the
black levels at the voltage outputs (pins 19, 16 and 13) are
set internally to typical 0.5 V, 3 V DC at signal inputs
(pins 2, 5 and 8).
handbook, full pagewidth
OSD
fast blanking
contrast
100 pF
1 kΩ
4.7 kΩ
PH2222
20
channel 1
17
channel 2
TDA4884
6
14
current
output
BFQ235
PH2222
channel 3
220 Ω
OSD
signal input
150 Ω
depending on
channel gain
1 kΩ to 10 kΩ
MHA919
1997 Nov 26
Fig.3 OSD application.
6