TDA4884 Datasheet, PDF (20/28 Pages) NXP Semiconductors – Advanced monitor video controller for OSD

Philips Semiconductors
Three gain control video pre-amplifier for OSD
Product specification
TDA4884
11 APPLICATION AND TEST INFORMATION
For high frequency measurements and special application,
a printed-circuit board with only a few external
components is built. Figure 17 shows the application
circuit and Fig.18 the layout of the double sided printed
board. All components on the underside and R13, R14 and
R15 on the top are SMD types. Short HF loops and
minimum crosstalk between the channels as well as input
and output are achieved by properly shaped ground areas
star connected to the IC ground pin.
The HF input signal can be fed to the subclick connectors
P1, P2 and P3 by a 50 Ω line. The line is then terminated
by a 51 Ω resistor on the board. With choice of jumper
connections (J1, J2 and J3) it is possible to connect
channel inputs to its input connector, to connect all
channels to one input connector (white pattern) and to
ground each input via the coupling capacitor.
For operation without input clamping (e.g. test mode) the
DC bias can be provided by VIDC (connector P21) if a
short-circuit at J4, J5 and J6 is made (solder short or
low-value SMD resistor).
The output signal can be monitored via 50 Ω terminated
lines at the voltage outputs (subclick connectors
P4, P5 and P6). With 100 Ω in parallel to the 50 Ω
terminated line the effective load resistance at the voltage
outputs is 33 Ω. The mismatch seen from the line towards
the IC has no significant effect if the line is match
terminated. A peaking circuit (C15, R16 for channel 1,
C16, R17 for channel 2 and C17, R18 for channel 3) can
be added for realistic loading of the voltage outputs.
Black-level adjustment is made by VIOS, VFBX (external
voltages at connector P21) and resistors R19, R22 and
R25 for channel 1 (channel 2: R20, R23 and R26;
channel 3: R21, R24 and R27). If R19 is equal to the
effective load resistor at the voltage output the reference
black level (V_ref(bl)) is approximately:
V_ref(bl) = VIOS – V_ref(int) – ( V_ref(int) – VFBX) × ^{RR-----22----25-}
V_ref(int) is the internal reference voltage at the feedback
input (typical 5.8 V). By this it is possible to adjust the
reference black level and the voltage at the current outputs
independently.
DC control for contrast and gain is provided at connectors
P21 and P22. Contrast control can also be set by the
potentiometer R28 (jumper J11). The series resistor R11 is
necessary if fast OSD switching is activated via 50 Ω line
(P10), a line termination can be provided at the connector
P9. Clamping and blanking pulses are fed to the IC via
connectors P7 and P8. Connector P23 is used for power
supply. The capacitors C7 and C8 should be located as
near as possible to the IC pins.
11.1 Recommendations for building the application
board
• General
– Double-sided board
– Short HF loops by large ground plane on the rear.
• Voltage outputs
– Capacitive loads as small as possible
– Short interconnection via resistor to ground.
• Supply voltage
– Capacitors as near as possible to the pins
– Use of high-frequency capacitors (low self
inductance, e.g. SMD).
• Current outputs, emitter of cascode transistors
The external interconnection inductance can build a
resonance together with the internal substrate
capacitance. A damping resistor of 10 to 30 Ω near to
the IC pin can suppress such oscillations.
1997 Nov 26
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