TDA4882 Datasheet, PDF (6/28 Pages) NXP Semiconductors – Advanced monitor video controller for OSD

Philips Semiconductors
Advanced monitor video controller for OSD
Product specification
TDA4882
7.5 Input clamping
The clamping pulse (Fig.17) is for input clamping only.
The input signals are at black level during the clamping
pulse and are clamped to an internal artificial black level.
The coupling capacitors provide black-level storage.
The threshold for the clamping pulse is higher than that for
vertical blanking, therefore, the rise and fall times of the
clamping pulse need to be faster than 75 ns/V during
transition from 1 to 3.5 V.
7.6 Vertical blanking
The vertical blanking pulse (Fig.17) will be detected if the
input voltage is higher than the threshold voltage for
approximately 320 ns but does not exceed the threshold
for the clamping pulse in the time between. During the
vertical blanking pulse the input clamping is disabled to
avoid misclamping in the event of composite input signals.
The input signal is blanked and the artificial black level is
inserted instead. Also the brightness is set internally to its
nominal value, thus the output signal is at reference black
level. The DC value of the reference black level will be
adjusted by cut-off stabilization.
7.7 Horizontal blanking
During horizontal blanking (Fig.18) the output signal is set
to reference black level and output clamping is activated.
If the voltage exceeds the switch-off threshold, the signal
is blanked and switched to ultra-black level for screen
protection and spot suppression during V-flyback.
Ultra-black level is the lowest possible channel output
voltage and is not dependent on cut-off stabilization.
7.8 Cut-off and black-level stabilization
For cut-off stabilization (DC coupling to the CRT) and
black-level stabilization (AC coupling) the video signal at
the cathode or the coupling capacitor is divided by an
adjustable voltage divider and fed to the channel feedback
inputs. During horizontal blanking time this signal is
compared with an internal DC voltage of approximately
5.8 V. Any difference will lead to a reference black-level
correction by charging or discharging the integrated
capacitor which stores the reference black-level
information between the horizontal blanking pulses.
7.9 On Screen Display
For OSD (Fig.3), fast switching of control pin 6 to less than
1 V (e.g. 0.7 V) blanks the input signals. The OSD signals
can easily be inserted to the external cascode transistor.
7.10 Test mode
During test mode (pins 9 and 10 connected to V_P) the
black levels at the channel voltage outputs are set
internally to typical 0.7 V with nominal brightness and
3 V DC at channel signal inputs.
handbook, full pagewidth
OSD
fast blanking
1997 Sep 04
contrast
100 pF
1 kΩ
4.7 kΩ
PH2222
20
channel 1
17
channel 2
TDA4882
6
14
current
output
Fig.3 OSD application.
6
BFQ235
PH2222
channel 3
220 Ω
OSD
signal input
150 Ω
depending on
channel gain
1 kΩ to 10 kΩ
MHA816