TDA4882 Datasheet, PDF (12/28 Pages) NXP Semiconductors – Advanced monitor video controller for OSD

Philips Semiconductors
Advanced monitor video controller for OSD
Product specification
TDA4882
11. The signal-to-noise ratio is calculated by the formula (frequency range 1 to 70 MHz):
N-S-- ^{= 20 × log p----e---a----k------t-o-------pR---e--M-a----kS----v--v-a--a--l-lu-u--e--e---o--o--f-f--t-t-h-h--e-e----n-n---o-o--m-i-s---ie-n----ao---l-u--s-t--pi-g--u--n-t--a--v-l--o-o--l--tu-a--t--gp---eu---t---v---o----l-t--a---g---e-- dB}
12. Large output swing e.g. I_o(b-w) = 50 mA leads to signal-dependent power dissipation in output transistors.
Thermal V_BE variation is compensated.
13. Composite signals will not disturb normal operation because an internal clipping circuit cuts all signal parts below
black level.
14.
The output current approximately follows the equation
I_o
=
V_o


R---1--_O^--
+
2----.--2--1---k---Ω^---


– 500
µA
for V_o > V_bl(SO) and with
R_O = external resistor at voltage output to ground. The external RC combination (Fig.1) at pins 19, 16 and 13
(voltage outputs) enables peak currents during transients.
15. Frequency response, crosstalk and pulse response have been measured at voltage outputs on a special
printed-circuit board with 50 Ω line in/out connections and without peaking, see Chapter 11.
16. Crosstalk between any two voltage outputs (e.g. channels 1 and 2).
a) Input conditions: one channel (channel 1) with nominal input signal and minimum rise time. The inputs of the
other channels capacitively coupled to ground (channels 2 and 3). Gain pins 3 and 11 open-circuit.
b) Output conditions: output signal of channel 1 is set by contrast control voltage, to V_o(b-w) = V_o(VOUT1) = 0.7 V,
the rise time should be 5 ns. Output signal of channel 2 then is V_o(b-w) = V_o(VOUT2).
c) Transient crosstalk: α_ct(tr) = 20 × log ^VV-----oo--⁽⁽--^VV---^OO---^UU----^TT--²¹---⁾⁾ dB
d) Crosstalk as a function of frequency has been measured without peaking circuit, with nominal input signal and
nominal settings.
17. The internal threshold voltages are derived from a stabilized voltage. The internal pulses are generated while the
input pulses are higher than the thresholds. Voltages less than −0.1 V at pins 9 and 10 can influence black-level
control and should be avoided.
18. The delay between HBL input pulse (horizontal blanking) and output signal blanking pulse and also brightness
blanking (∆V_bl), at the voltage outputs, depends on the input rise time of the HBL pulse. The specified values for
t_d(Hblank) are valid for HBL rise times greater than 100 ns only.
19. For 75 ns/V < t_r(CL), t_f(CL) < 240 ns/V, generation of internal input clamping and blanking pulse is not defined. Pulses
not exceeding the threshold of input clamping (typical 3 V) will be detected as blanking pulses.
1997 Sep 04
12