TDA4820T Datasheet, PDF (6/10 Pages) NXP Semiconductors – Sync separation circuit for video applications

Philips Semiconductors
Sync separation circuit for video applications
Preliminary specification
TDA4820T
CHARACTERISTICS
All voltages measured to GND (pin 8); V_P = 12 V; T_amb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP.
V_P
supply voltage range (pin 1)
I_P
supply current (pin 1)
10.8 12.0
4
8
Video amplifier
V_2(p-p)
V_{sync (p-p)}
input amplitude
(peak-to-peak value)
sync pulse amplitude (pin 2)
(peak-to-peak value)
Z_s
source impedance
Black level clamping
positive video signal
AC coupled
0.2 1
composite sync slicing 50
300
level 50% for
0.2 V ≤ V_2(p-p) ≤ 1.5 V
−
−
I₂
discharge current of C2
during video content
−
5
charge currents of C2
sync below slicing level −
−40
sync above slicing level −
−25
during black level
−
−20
50% peak sync voltage
I₃
discharge current of C3
during video content
−
16
maximum charge current of C3
−
−345
reduced charge current of C3
during vertical sync
−
−255
charge current of C3
during sync pulse
−
−160
Composite sync slicing (see Fig.4)
composite sync slicing level
t_dH
horizontal delay time (pin 7)
Vertical sync separation (see Fig.5)
0.2 V ≤ V_2(p-p) ≤ 1.5 V
−
50
maximum load at pin 7: −
250
C_L ≤ 5 pF; R_L ≥ 100 kΩ
slicing level for vertical sync
0.2 V ≤ V_2(p-p) ≤ 1.5 V
−
40
t_dV
vertical leading edge delay times pin 4 open
30
45
(pin 6)
pin 4 grounded
11
18
Vertical and composite sync outputs
V_o
maximum vertical sync
I₆ = −1 mA
output voltage (pin 6)
10.0 10.5
V_o
maximum composite sync
I₇ = −3 mA
output voltage (pin 7)
10.0 10.5
V_o
minimum output voltages
I_6,7 = 1 mA
(pins 6 and 7)
0.1 0.3
t_W
vertical sync pulse width
pin 4 open; standard
−
180
signal of 625 lines
MAX.
13.2
12
UNIT
V
mA
3
V
500
mV
200
Ω
−
µA
−
µA
−
µA
−
µA
−
µA
−
µA
−
µA
−
µA
−
%
500
ns
−
%
60
µs
25
µs
11.5
V
11.5
V
0.6
V
−
µs
June 1990
6