TDA4820T Datasheet, PDF (4/10 Pages) NXP Semiconductors – Sync separation circuit for video applications

Philips Semiconductors
Sync separation circuit for video applications
Preliminary specification
TDA4820T
FUNCTIONAL DESCRIPTION
The complete circuit consists of the following functional
blocks as shown in Fig.1:
– Video amplifier and black level clamping
– 50% peak sync voltage
– Composite sync slicing
– Vertical slicing and double slope integrator
– Vertical sync output
– Composite sync output
Video amplifier and black level clamping (pin 2)
The sync separation circuit TDA4820T is designed for
positive video input signals.
The video signal (supplied via capacitor C2 at pin 2) is
amplified by approximately 15 in the input amplifier. The
black level clamping voltage (approximately 2 V) is stored
by capacitor C2.
50% peak sync voltage (pin 3)
From the black level and the peak sync voltage, the 50%
value of the peak sync voltage is generated and stored by
capacitor C3 at pin 3. A slicing level control circuit ensures
a constant 50% value, as long as the sync pulse amplitude
at pin 2 is between 50 mV and 500 mV, independent of the
amplitude of the picture content.
Composite sync slicing
A comparator in the composite sync slicing stage
compares the amplified video signal with the DC voltage
derived from 50% peak sync voltage. This generates the
composite sync output signal.
Vertical slicing and double slope integrator
Vertical slicing compares the composite sync signal with a
DC level equal to 40 % of the peak sync voltage, similar to
the composite sync slicing.
With signal interference (reflections or noise) the reduced
vertical slicing level ensures more energy for the vertical
pulse integration. The slope is double-integrated to
eliminate the influence of signal interference.
The vertical integration delay time t_dV can be set from
typically 45 µs (pin 4 open) to typically 18 µs (pin 4
grounded).
Between these maximum and minimum values, t_dV can be
set by a resistor R1 from pin 4 to ground. For optimum
sync behaviour with input line sync pulses only, R1 has to
be ≥ 3.3 kΩ. In this case t_dV is typically ≥ 23 µs.
Vertical sync output Composite sync output
Both output stages are emitter followers with bias currents
of 2 mA.
June 1990
Fig.3 Internal circuits.
4