SAA7360 Datasheet, PDF (6/20 Pages) NXP Semiconductors – Bitstream conversion ADC for digital audio systems

Philips Semiconductors
Bitstream conversion ADC
for digital audio systems
Product specification
SAA7360
FUNCTIONAL DESCRIPTION
General
The SAA7360 is a bitstream conversion CMOS ADC for
digital audio systems. The device consists of a input buffer
which can be configured by the user for pre-scaling and
anti-aliasing, a third order Sigma- Delta modulator with a
performance of better than 90 dB THD + Noise, and
decimation filters with anti-aliasing suppression of >93 dB
and in band ripple of less than 0.0002 dB. The device
outputs data in a number of formats compatible with a
range of manufacturers.
Clock frequency
The SAA7360 can operate in either master or slave mode
(CMOS input drive levels). The clock can be either 256f_s or
512f_s (where f_s is the sampling frequency) indicated via pin
FSEL. System clock outputs equal to the input frequency
(XSYS1) and half the input frequency (XSYS2) are
provided to drive other ICs in the system. All performance
parameters track with f_s which can vary between
18 and 53 kHz without degradation of performance.
Input buffer
The input buffer stage consists of an uncommitted input
operational amplifier (‘A’) and a committed unity gain
operational amplifier (‘B’) to perform a single-to-double
ended conversion for the differential ADC. The input buffer
can be configured for pre-scaling and second order
anti-aliasing filtering. The scaling should be performed so
as to provide a maximum of 1 V RMS value at the output
of the operational amplifier.
Sigma-Delta modulator
The analog-to-digital conversion is performed by a third
order Sigma-Delta modulator, which outputs a 1-bit code
at 128f_s with a distortion plus noise figure of >90 dB. The
modulator is scaled so that a 0 dB input results in an output
of −3 dB, at the 1-bit outputs.
Digital decimation filter
The left and right channel 1-bit codes from the ADC are
decimated from 128f_s to 1f_s in four stages of filtering. The
first filter stage decimates by a factor of 16f_s to 8f_s using a
4th order combination type filter. The other three filter
stages consist of three cascaded half-band filters each
decimating by a factor of two. The half-band filter
decimating from 8f_s to 4f_s has a gain of +2 dB to
compensate for the −3 dB through the analog part and
allow a headroom of 1 dB to prevent clipping with DC
offsets.
The overall response of the digital decimation filter is a
pass band from 0f_s to 0.454f_s (20 kHz at f_s = 44.1 kHz)
with a ripple of <0.0002 dB and a transition band of
0.454f_s to 0.544f_s. All frequencies between
0.544f_s and 64f_s which could result in aliasing into the
base band are attenuated by >−93 dB.
High-pass filter
The operational amplifiers in the Sigma-Delta modulator
can cause a small DC offset to be present in the 1-bit code
passed to the digital section. This can result in the
possibility of clicks when switching between devices and
the recording of DC offsets which can upset offsets
introduced in filters and noise shaping DACs in the
playback path. A switchable high-pass filter is included on
the IC after the decimation filter stage to allow the user to
remove these DC offsets (selectable via pin HPEN). The
filter does not affect the decimation process. The filter is
1st order high pass with following specifications:
• Corner frequency (−3 dB): 1.7 Hz
• Ripple: none
• Above 100 Hz: <0.00002 dB; <1 degree
• At 20 Hz: −0.03 dB, 5 degree phase deviation
• Noise floor: −116 dB.
Output interface
The output interface can operate in master or slave mode
selectable by pin TSEL. Master mode drives pins SWSO
(word select), SCKO (bit clock) and SDO (data output).
Slave mode receives the word clock on pin SWSI and the
bit clock on pin SCKI. In slave mode the internal circuitry
runs on the incoming bit clock and therefore cannot
operate with burst clocks. Slave mode causes the pins
SWSO and SCKO to be 3-stated allowing systems to
connect SWSO and SCKO to pins SWSI and SCKI
respectively for applications where the device has to
operate in master and slave modes. The bit clock in master
mode is at 32f_s for 16-bit output, and 64f_s for 18-bit output.
In slave mode the bit clock is a minimum of 32f_s and a
maximum of 64f_s.
Three output formats are supported, I²S and two pseudo
I²S modes common in digital audio ADC systems. These
formats are shown in Fig.3. Selection of the three formats
is given in Table 1. 16-bit or 18-bit output words can be
chosen (via pin WSEL).
1995 Apr 24
6