SA572 Datasheet, PDF (6/12 Pages) NXP Semiconductors – Programmable analog compandor

Philips Semiconductors
Programmable analog compandor
Product specification
SA572
Rectifier
The rectifier is a full-wave design as shown in Figure 5. The input
voltage is converted to current through the input resistor R₂ and
turns on either Q₅ or Q₆ depending on the signal polarity. Deadband
of the voltage to current converter is reduced by the loop gain of the
gain block A₂. If AC coupling is used, the rectifier error comes only
from input bias current of gain block A₂. The input bias current is
typically about 70nA. Frequency response of the gain block A₂ also
causes second-order error at high frequency. The collector current
of Q₆ is mirrored and summed at the collector of Q₅ to form the full
wave rectified output current I_R. The rectifier transfer function is
I_R
+
V_IN
* V_REF
R₂
(4)
If V_IN is AC-coupled, then the equation will be reduced to:
I_RAC
+
V_IN(AVG)
R₂
The internal bias scheme limits the maximum output current I_R to be
around 300µA. Within a ±1dB error band the input range of the rectifier
is about 52dB.
V+
IR
+
VIN * VREF
R2
V_REF
+
A2
–
Q5
R2
V_IN
D7
Q6
Buffer Amplifier
In audio systems, it is desirable to have fast attack time and slow
recovery time for a tone burst input. The fast attack time reduces
transient channel overload but also causes low-frequency ripple
distortion. The low-frequency ripple distortion can be improved with
the slow recovery time. If different attack times are implemented in
corresponding frequency spectrums in a split band audio system,
high quality performance can be achieved. The buffer amplifier is
designed to make this feature available with minimum external
components. Referring to Figure 6, the rectifier output current is
mirrored into the input and output of the unipolar buffer amplifier A₃
through Q₈, Q₉ and Q₁₀. Diodes D₁₁ and D₁₂ improve tracking
accuracy and provide common-mode bias for A₃. For a
positive-going input signal, the buffer amplifier acts like a
voltage-follower. Therefore, the output impedance of A₃ makes the
contribution of capacitor CR to attack time insignificant. Neglecting
diode impedance, the gain Ga(t) for ∆G can be expressed as
follows:
*t
Ga(t) + (Ga_INT * Ga_FNL e ^tA ) Ga_FNL
Ga_INT=Initial Gain
Ga_FNL=Final Gain
τ_A=R_A • CA=10k • CA
where τ_A is the attack time constant and R_A is a 10k internal
resistor. Diode D₁₅ opens the feedback loop of A₃ for a
negative-going signal if the value of capacitor CR is larger than
capacitor CA. The recovery time depends only on CR • R_R. If the
diode impedance is assumed negligible, the dynamic gain G_R (t) for
∆G is expressed as follows.
*t
G_R(t) + (G_RINT * G_RFNL e^tR ) G_RFNL
G_R(t)=(G_{R INT}–G_{R FNL}) e +G_{R FNL}
τR=R_R • CR=10k • CR
where τR is the recovery time constant and R_R is a 10k internal
resistor. The gain control current is mirrored to the gain cell through
Q₁₄. The low level gain errors due to input bias current of A₂ and A₃
can be trimmed through the tracking trim pin into A₃ with a current
source of ±3µA.
SR00698
Figure 5. Simplified Rectifier Schematic
1998 Nov 03
6