R_10032 Datasheet, PDF (6/10 Pages) NXP Semiconductors – CA-330-11 LDMOS bias module

NXP Semiconductors
R_10032
CA-330-11; LDMOS bias module
5
Z_o
(Ω)
4
3
2
1
0
10^-1
1
V_DC = 1.8 V; P_AC = 10 dBm (50 ).
Fig 3. Output impedance of bias module
aaa-004140
10
10²
f (MHz)
1
2
L1
V+
3 ^BLM21BD102
C5
2.2 μF
U1
IN
8
1 ^OUT
LT3010EMS8E
R1
10 kΩ
EN
5
2 ^ADJ
GND: 4, 9
Fig 4. Bias module schematic
+8 V
R2
52.3 kΩ
R3
10 kΩ
C4
1 nF
C3
1 μF
D1
HSMG-C150
green = power
R6
1.1 kΩ
R7
432 Ω
R4
432 Ω
R5
200 Ω
3
2 ^R8
2 kΩ
1
R9
75 Ω
R13
1.1 kΩ
R10
10 kΩ
U2
LM7321MF
3
5
1
C2
42
100 nF
C7
100 nF
R12
5.11 kΩ
R11
909 Ω
4
temperature
5
compensation
6 _{npn transistor}
C1
1 μF
7
VGATE 8
VG
9
C6
1 μF
aaa-004141
R_10032
Report
Table 2. Bias module bill of materials
See Figure 5 and Figure 6 for component layout.
Component Description
C1, C3, C6 capacitor; 50 V 10 % X7R, 0805
C2, C7
capacitor; 50 V 10 % X7R, 0805
C4
capacitor; 100 V 10 % NP0, 0805
C5
capacitor; 100 V 10 % X7R, 1210
D1
LED; green, 1206
L1
ferrite bead; 200 mA, 0805
R1, R3, R10 resistor; 1 % 100 ppm CF, 0805
R2
resistor; 1 % 100 ppm CF, 0805
R4, R7
resistor; 1 % 100 ppm CF, 0805
Value
1 F
100 nF
1 nF
2.2 F
Remarks
Murata BLM21BD102SN1D
10.0 k
52.3 k
432 
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 24 July 2012
© NXP B.V. 2012. All rights reserved.
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