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| PSMN2R0-30YLE_15 Datasheet, PDF (6/13 Pages) NXP Semiconductors – -channel 30 V 2 mΩ logic level MOSFET in LFPAK | |||
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NXP Semiconductors
PSMN2R0-30YLE
N-channel 30 V 2 m⦠logic level MOSFET in LFPAK
Symbol
Parameter
Conditions
RG
internal gate
f = 1 MHz
resistance (AC)
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 15 V; VGS = 10 V;
Fig. 14; Fig. 15
ID = 25 A; VDS = 15 V; VGS = 4.5 V;
Fig. 14; Fig. 15
ID = 0 A; VDS = 0 V; VGS = 10 V
QGS
QGS(th)
gate-source charge
pre-threshold gate-
source charge
ID = 25 A; VDS = 15 V; VGS = 4.5 V;
Fig. 14; Fig. 15
QGS(th-pl)
post-threshold gate-
source charge
QGD
gate-drain charge
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 15 V; Fig. 14; Fig. 15
Ciss
input capacitance
VDS = 15 V; VGS = 0 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; Fig. 16
Crss
reverse transfer
capacitance
td(on)
tr
turn-on delay time
rise time
VDS = 15 V; RL = 0.6 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω; Tj = 25 °C
td(off)
turn-off delay time
tf
fall time
Source-drain diode
VSD
source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 17
trr
reverse recovery time IS = 25 A; dIS/dt = 100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 15 V
Min Typ Max Unit
0.3 0.6 1.2 Ω
-
87
-
nC
-
41
-
nC
-
79
-
nC
-
13.3 -
nC
-
8.1 -
nC
-
5.2 -
nC
-
13.8 -
nC
-
2.8 -
V
-
5217 -
pF
-
1015 -
pF
-
474 -
pF
-
32.7 -
ns
-
55.7 -
ns
-
41.5 -
ns
-
29.5 -
ns
-
0.8 1.2 V
-
42.6 -
ns
-
49.8 -
nC
PSMN2R0-30YLE
Product data sheet
All information provided in this document is subject to legal disclaimers.
12 October 2012
© NXP B.V. 2012. All rights reserved
6 / 13
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