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| BLC8G20LS-310AV_15 Datasheet, PDF (6/15 Pages) NXP Semiconductors – Power LDMOS transistor | |||
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NXP Semiconductors
BLC8G20LS-310AV
Power LDMOS transistor
Table 13. Typical impedance of peak device at 1 : 1 load
Measured load-pull data of peak device; IDq = 1200 mA (peak); VDS = 28 V; pulsed CW (tp = 100 ïs;
ï¤ = 10 %).
f
(MHz)
ZS [1]
(ï)
ZL [1]
(ï)
PL [2]
(dBm)
ï¨D [2]
(%)
Gp [2]
(dB)
Maximum power load
1930
1.1 ï j4.9
1.7 ï j4.9
231.2
51.9
16.6
1962
1.4 ï j4.1
1.6 ï j4.7
217.8
53.0
17.3
1995
1.8 ï j4.4
1.6 ï j4.5
215.3
57.1
17.9
[1] ZS and ZL defined in Figure 1.
[2] at 3 dB gain compression.
Table 14.
f
(MHz)
1930
1962
1995
Off-state impedances of peak device
Zoff
(ï)
0.6 + j1.9
0.6 + j2.2
0.6 + j2.5
7.4 Test circuit
PP
BLC8G20LS-310AV
Product data sheet
PP
5
&
&
5
&
;
5
&
&
&
5 5
&
&
&
&
&
&
&
&
&
&
&
&
&
Fig 2.
Printed-Circuit Board (PCB): Rogers RO4350B; thickness = 0.508 mm;
thickness copper plating = 35 ïm. See Table 15 for a list of components.
Component layout for test circuit
DDD
All information provided in this document is subject to legal disclaimers.
Rev. 2 â 6 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 15
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