ISP1581 Datasheet, PDF (52/73 Pages) NXP Semiconductors – Universal Serial Bus 2.0 high-speed interface device

Philips Semiconductors
ISP1581
USB 2.0 HS interface device
12.3 Parallel I/O timing
12.3.1 Generic Processor mode (BUS_CONF = 1)
CS
AD [7:0]
(read) DATA[15:0]
RD
(write) DATA[15:0]
DS / WR
(I2)
R/W
(I1)
t _RLDV
t _AVRL
Tcy(RW)
t _WHSH
t _RHSH
t _WHAX
t _RHAX
t _RHDZ
t _AVWL
t _I1VI2L
t _WHDZ
t _DVWH
read
write
t _I2HI1X
Fig 11. Parallel I/O timing: separate address and data buses.
MGT497
Table 82: Parallel I/O timing parameters: separate address and data buses
Symbol Parameter
Min
Max
Reading
t_AVRL
address set-up time before RD LOW
0
-
t_RHAX
address hold time after RD HIGH
0
-
t_RLDV
RD LOW to data valid delay
-
35
t_RHDZ
RD HIGH to data outputs three-state delay 0
20
t_RHSH
RD HIGH to CS HIGH delay
0
-
Writing
t_AVWL
t_WHAX
t_DVWH
t_WHDZ
t_WHSH
address set-up time before WR LOW
address hold time after WR HIGH
data set-up time before WR HIGH
data hold time after WR HIGH
WR HIGH to CS HIGH delay
0
-
0
-
25
-
0
-
0
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9397 750 07648
Objective specification
Rev. 02 — 23 October 2000
© Philips Electronics N.V. 2000. All rights reserved.
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