ISP1581 Datasheet, PDF (12/73 Pages) NXP Semiconductors – Universal Serial Bus 2.0 high-speed interface device

Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Table 4: Register summary…continued
Name
Destination
DMA registers
DMA Command
DMA Transfer Counter
DMA Configuration
DMA controller
DMA controller
DMA controller
DMA Hardware
1F0 Task File
1F1Task File
1F2 Task File
1F3 Task File
1F4 Task File
1F5 Task File
1F6 Task File
1F7 Task File
3F6 Task File
3F7 Task File
DMA Interrupt Reason
DMA Interrupt Enable
DMA Endpoint
DMA Strobe Timing
General registers
Interrupt
Chip ID
Frame Number
Scratch
Unlock Device
Test Mode
DMA controller
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
DMA controller
DMA controller
DMA controller
DMA controller
device
device
device
device
device
PHY
Address
(Hex)
Description
Size
(bytes)
30
34
38 (byte 0)
39 (byte 1)
3C
40
48
49
4A
4B
4C
4D
44
4E
4F
50 (byte 0)
51 (byte 1)
54 (byte 0)
55 (byte 1)
58
60
controls all DMA transfers
1
sets byte count for DMA Transfer
4
sets GDMA configuration (counter enable, 1
burst length, data strobing, bus width)
sets ATA configuration (IORDY enable, 1
mode selection: ATA/UDMA/MDMA/PIO)
endian type, master/slave selection, signal 1
polarity for DACK, DREQ, DIOW, DIOR
single address word register: byte 0 (lower 2
byte) is accessed first
IDE device access
1
IDE device access
1
IDE device access
1
IDE device access
1
IDE device access
1
IDE device access
1
IDE device access (write only; reading 1
returns 00H)
IDE device access
1
IDE device access
1
shows reason (source) for DMA interrupt 1
1
enables DMA interrupt sources
1
1
selects endpoint FIFO, data flow direction 1
strobe duration in UDMA/MDMA mode 1
18
shows interrupt sources
4
70
product ID code and hardware version 3
74
last successfully received Start Of Frame: 2
lower byte (byte 0) is accessed first
78
allows save/restore of firmware status
2
during ‘suspend’
7C
re-enables register access after ‘suspend’ 2
84
direct setting of D+, D− states, loopback 1
mode, internal transceiver test (PHY)
9397 750 07648
Objective specification
Rev. 02 — 23 October 2000
© Philips Electronics N.V. 2000. All rights reserved.
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