TDA8421 Datasheet, PDF (5/26 Pages) NXP Semiconductors – Hi-fi stereo audio processor; I2C bus

Philips Semiconductors
Hi-fi stereo audio processor; I²C bus
Product specification
TDA8421
Headphone channel (CH2)
Volume control and balance
The stages for volume control for CH2 consist of two parts
for left and right. In each part the gain can be adjusted
between 0 and −62 dB in steps of 2 dB. An additional step
allows an attenuation of ≥ 90 dB. Both parts can be
controlled independently over the whole range, which
allows the balance to be varied by controlling the volume
of left and right.
Loudspeaker channel (CH1)
Volume control and balance
The loudspeaker channel (CH1) also consists of two parts
for volume control (left and right). In each part the gain
can be adjusted between + 16 dB and −62 dB in steps of
2 dB. An additional step allows an attenuation of ≥ 90 dB.
Both parts can be controlled independently over the
whole range, which allows the balance to be varied by
controlling the volume of left and right.
Stereo/pseudo stereo/spatial stereo mode
It is possible to select three modes. Stereo, pseudo or
spatial stereo. The pseudo stereo mode receives mono
transmissions and the stereo and spatial stereo mode
receives stereo transmissions.
Bass control
The bass control stage can be switched from an
emphasis of 15 dB to an attenuation of 12 dB for low
frequencies in steps of 3 dB.
Treble control
The treble control stage can be switched from + 12 dB to
−12 dB in steps of 3 dB.
Bias and power supply
The TDA8421 includes a bias and power supply stage,
which generates a voltage of ¹â„₂ V_CC with a low output
impedance and injector currents for the logic part.
Power-on reset
The on-chip power-on reset circuit sets the mute bit to
active, which mutes both the loudspeaker channel (CH1)
and the headphone channel (CH2). The muting can be
switched by transmission of the mute bit.
I²C bus receiver and data handling
Bus specification
The TDA8421 is controlled via the 2-wire I²C bus by a
microcomputer. The two wires (SDA - serial data, SCL -
serial clock) carry information between the devices
connected to the bus. Both SDA and SCL are bidirectional
lines, connected to a positive supply voltage via a pull up
resistor.
When the bus is free both lines are HIGH. The data on the
SDA line must be stable during the HIGH period of the
clock. The HIGH or LOW state of the data line can only
change when the clock signal on the SCL line is LOW.
The set up and hold times are specified in
AC CHARACTERISTICS.
A HIGH-to-LOW transition of the SDA line while SCL is
HIGH is defined as a start condition. A LOW-to-HIGH
transition of the SDA line while SCL is HIGH is defined as
a stop condition. The bus receiver will be reset by the
reception of a start condition. The bus is considered to be
busy after the start condition. The bus is considered to be
free again after a stop condition.
Module address
Data transmission to the TDA8421 starts with the module
address MAD.
Fig.3 TDA8421 module address.
The module address is determined by pin 16. When connected to ground MAD = 0; when connected to V_CC MAD = 1.
Thus two TDA8421s can be selected within a system.
May 1988
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