TDA4800 Datasheet, PDF (5/16 Pages) NXP Semiconductors – Vertical deflection circuit for monitor applications

Philips Semiconductors
Vertical deflection circuit for monitor
applications
Product specification
TDA4800
FUNCTIONAL DESCRIPTION
The complete circuit consists of the following functional
blocks as shown in Fig.1:
1. Oscillator
2. Synchronization circuit
3. Blanking pulse generator
4. Frequency detector and storage
5. Ramp generator
6. Buffer stage
7. Preamplifier
8. Power output stage
9. Flyback generator
10. Guard circuit
11. Voltage stabilizer.
Oscillator (pins 1 and 2)
The oscillator is an RC-oscillator with a threshold value
switch, which ensures very good frequency stability.
The upper and lower threshold voltages are defined by an
internal voltage divider.
An external capacitor C1 at pin 2 is charged by a constant
current source. When the scan voltage of C1 reaches the
upper threshold voltage, oscillator flyback starts. Capacitor
C1 discharges via an internal resistor and transistor until
the lower threshold is reached.
The constant charge current and free-running frequency f_o
are adjusted by an external resistor R1 at pin 1:
f_o = _K------×-----R----1-1----_×-----C-----1-- with K = 0.68.
Synchronization circuit (pin 3)
A positive- or negative-going pulse fed to pin 3
synchronizes the oscillator by lowering the upper threshold
voltage. The synchronizing range is f_o to 3f_o. For example:
f_o = 50 Hz → f_sync(max) = 150 Hz.
Blanking pulse generator (pin 3)
Also at pin 3 a blanking pulse is available. Diode D1
separates the synchronization pulse from the blanking
pulse. During scanning, the external capacitor C6 at pin 12
is charged to an internal stabilized voltage V_stab2.
The blanking pulse starts with the beginning of oscillator
flyback; then capacitor C6 discharges via the external
resistor R13 at pin 12. The blanking pulse stops when the
capacitor voltage is ¹â„₂V_stab2.
The blanking pulse duration is determined by the values of
external components R13 and C6 at pin 12:
t_bl = R13 × C6 × Ln2.
Frequency detector with storage (pin 13)
At the end of the scanning period a frequency detector
detects the oscillator frequency (see “Note” below).
When this frequency is above the threshold a flip-flop is set
to store this information. The output is an open collector
output.
NOTE
Frequency detector change-over at pin 13 from low (= low
frequency) to high (= high frequency) is determined by f_o:
f_threshold = 1.23 × f_o.
Ramp generator (pin 11)
The ramp generator consists of two external series
capacitors C4 and C5, external charge resistor R12
(connected to pin 11), and an internal differential amplifier
which is synchronously switched by the oscillator.
External capacitors C4 and C5 at pin 11 are charged by
the charging current via the external charge resistor R12
until oscillator flyback starts. C4 and C5 are then
discharged via pin 11 by an internal resistor and transistor.
This generates a positive-going ramp voltage.
Buffer stage (pin 4)
The buffer stage consists of two emitter followers.
The ramp voltage is fed via the buffer stage and is
available at pin 4 with a low ohmic output impedance. With
R4 and P1 it generates a ramp function, which, together
with the feedback network of the deflection yoke, gives a
high degree of linearity at the picture tube. The linearity
can be adjusted by P1.
Preamplifier (pin 5)
The preamplifier is a differential amplifier.
The non-inverting input is fixed at about 2 V by an internal
voltage divider. The inverting input at pin 5 is connected to
the ramp voltage via R3 and feedback network P2,
R5 to R11, R15, R16, C7, C10 and C11.
Power output stage (pin 7)
The power output stage is an amplifier with a
quasi-complementary class-B output. The output is
connected to pin 7.
The power stage includes SOAR and thermal protection.
1997 Mar 27
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