SC26C94 Datasheet, PDF (5/33 Pages) NXP Semiconductors – Quad universal asynchronous receiver/transmitter QUART

Philips Semiconductors
Quad universal asynchronous receiver/transmitter (QUART)
Product specification
SC26C94
Table 1. QUART Registers¹
A5:0
READ (RDN = Low)
000000
Mode Register a (MR0a, MR1a, MR2a)
000001
Status Register a (SRa)
000010
Reserved
000011
Receive Holding Register a (RxFIFOa)
000100
Input Port Change Reg ab (IPCRab)
000101
Interrupt Status Reg ab (ISRab)
000110
Counter/Timer Upper ab (CTUab)
000111
Counter/Timer Lower ab (CTLab)
001000
Mode Register b (MR0b, MR1b, MR2b)
001001
Status Register b (SRb)
001010
Reserved
001011
Receive Holding Register b (RxFIFOb)
001100
Output Port Register ab (OPRab)
001101
Input Port Register ab (IPRab)
001110
Start Counter ab
001111
Stop Counter ab
010000
Mode Register c (MR0c, MR1c, MR2c)
010001
Status Register c (SRc)
010010
Reserved
010011
Receive Holding Register c (RxFIFOc)
010100
Input Port Change Reg cd (IPCRcd)
010101
Interrupt Status Reg cd (ISRcd)
010110
Counter/Timer Upper cd (CTUcd)
010111
Counter/Timer Lower cd (CTLcd)
011000
Mode Register d (MR0d, MR1d, MR2d)
011001
Status Register d (SRd)
011010
Reserved
011011
Receive Holding Register d (RxFIFOd)
011100
Output Port Register cd (OPRcd)
011101
Input Port Register cd (IPRcd)
011110
Start Counter cd
011111
Stop Counter cd
100000
Bidding Control Register a (BCRa)
100001
Bidding Control Register b (BCRb)
100010
Bidding Control Register c (BCRc)
100011
Bidding Control Register d (BCRd)
100100
Reserved
100101
Reserved
100110
Reserved
100111
Reserved
101000
Current Interrupt Register (CIR)
101001
Global Interrupting Channel Reg (GICR)
101010
Global Int Byte Count Reg (GIBCR)
101011
Global Receive Holding Reg (GRxFIFO)
101100
Interrupt Control Register (ICR)
101101
Reserved
101110
Reserved
101111
Reserved
110000–111000 Reserved
111001
Test Mode
111010–111111 Reserved
WRITE (WRN = Low)
Mode Register a (MR0a, MR1a, MR2a)
Clock Select Register a (CSRa)
Command Register a (CRa)
Transmit Holding Register a (TxFIFOa)
Auxiliary Control Reg ab (ACRab)
Interrupt Mask Reg ab (IMRab)
Counter/Timer Upper Reg ab (CTURab)
Counter/Timer Lower Reg ab (CTLRab)
Mode Register b (MR0b, MR1b, MR2b)
Clock Select Register b (CSRb)
Command Register b (CRb)
Transmit Holding Register b (TxFIFOb)
Output Port Register ab (OPRab)
I/OPCRa (I/O Port Control Reg a)
I/OPCRb (I/O Port Control Reg b)
Reserved
Mode Register c (MR0c, MR1c, MR2c)
Clock Select Register c (CSRc)
Command Register c (CRc)
Transmit Holding Register c (TxFIFOc)
Auxiliary Control Reg cd (ACRcd)
Interrupt Mask Reg cd (IMRcd)
Counter/Timer Upper Reg cd (CTURcd)
Counter/Timer Lower Reg cd (CTLRcd)
Mode Register d (MR0d, MR1d, MR2d)
Clock Select Register d (CSRd)
Command Register d (CRd)
Transmit Holding Register d (TxFIFOd)
Output Port Register cd (OPRcd)
I/OPCRc (I/O Port Control Reg c)
I/OPCRd (I/O Port Control Reg d)
Reserved
Bidding Control Register a (BCRa)
Bidding Control Register b (BCRb)
Bidding Control Register c (BCRc)
Bidding Control Register d (BCRd)
Power Down
Power Up
Disable DACKN
Enable DACKN
Reserved
Interrupt Vector Register (IVR)
Update CIR
Global Transmit Holding Reg (GTxFIFO)
Interrupt Control Register (ICR)
BRG Rate. 00 = low; 01 = high
Set X1/CLK divide by two²
Set X1/CLK Normal²
Reserved
Test Mode
Reserved
1995 May 1
5