SC26C94 Datasheet, PDF (24/33 Pages) NXP Semiconductors – Quad universal asynchronous receiver/transmitter QUART

Philips Semiconductors
Quad universal asynchronous receiver/transmitter (QUART)
Product specification
SC26C94
AC ELECTRICAL CHARACTERISTICS¹
T_A = 25°C; V_CC = 5V ± 10%, unless otherwise specified. Limits shown as nn/nn refer to Commercial/Industrial temperature range. Single
numbers apply to both ranges.
NO. FIGURE
CHARACTERISTIC
1
2
A[5:0] Setup time to RDN WRN Low
2
2
A[5:0] Hold time from RDN WRN Low
3
2
CEN Setup time to RDN WRN Low²
4
2
CEN Hold time from RDN WRN High²
5
2
RDN WRN Pulse Width Low
6
2
D[7:0] Data Valid after CEN and RDN Low
7
2
D[7:0] Data Bus floating after RDN or CEN High
8
2
D[7:0] Data Bus Setup time before WRN or CEN High
9
2
D[7:0] Hold time after WRN or CEN High
10
2
Time between Reads and/or Writes³
Min
10
45
0
0
110/115
40
8
50
LIMITS
Typ
Max
110/115
30
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating
supply range.
2. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as a ‘strobing’ input. CEN and
RDN (also CEN and WRN) are ANDed internally. As a consequence the signal asserted last initiates the cycle; the signal negated first
terminates the cycle. Address is latched at leading edge of a read or write cycle.
3. The RDN signal must be negated for this time to guarantee that internal registers update before the next read.
READ CYCLE
WRITE CYCLE
A[5:0]
1
2
1
2
CEN
RDN
WRN
D[7:0]
3
5
6
10
4
7
9
5
8
Figure 2. A Read Cycle Followed by a Write Cycle without DACKN
SD00164
1995 May 1
24