PHP3N20L Datasheet, PDF (5/7 Pages) NXP Semiconductors – PowerMOS transistor Logic level FET

Philips Semiconductors
PowerMOS transistor
Logic level FET
Product specification
PHP3N20L
10 ^{VGS, Gate-Source voltage (Volts)}
ID = 3.3 A
Tj = 25 C
8
VDS = 40 V
100 V
6
PHP2N20L
160 V
4
2
0
0
5
10
15
Qg, Gate charge (nC)
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G); parameter V_DS
Switching times (ns)
1000
VDD = 100 V
VGS = 5 V
RD = 30 Ohms
ID = 3.3 A
100 ^{Tj = 25 C}
td(off)
tf
tr
10 _td(on)
PHP2N20L
1
0
20
40
60
80
100
RG, Gate resistance (Ohms)
Fig.14. Typical switching times.
t_d(on), t_r, t_d(off), t_f = f(R_G)
Normalised Drain-source breakdown voltage
1.15
V(BR)DSS @ Tj
V(BR)DSS @ 25 C
1.1
1.05
1
0.95
0.9
0.85
-100
-50
0
50
100
150
Tj, Junction temperature (C)
Fig.15. Normalised drain-source breakdown voltage.
V_(BR)DSS/V_{(BR)DSS 25 ˚C} = f(T_j)
IF, Source-drain diode current (Amps)
20
VGS = 0 V
15
PHP2N20L
10
Tj = 175 C
Tj = 25 C
5
0
0
0.5
1
1.5
2
VSDS, Source-drain voltage (Volts)
Fig.16. Source-Drain diode characteristic.
I_F = f(V_SDS); parameter T_j
EAS, Normalised unclamped inductive energy (%)
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140 160 180
Starting Tj ( C)
Fig.17. Normalised unclamped inductive energy.
E_AS% = f(T_j)
VGS
0
RGS
L
VDS
T.U.T.
+ ^VDD
-
-ID/100
R 01
shunt
Fig.18. Unclamped inductive test circuit.
E_AS = 0.5 ⋅ LI_D² ⋅ V_(BR)DSS/(V_(BR)DSS − V_DD)
September 1997
5
Rev 1.000