PHP3N20L Datasheet, PDF (3/7 Pages) NXP Semiconductors – PowerMOS transistor Logic level FET

Philips Semiconductors
PowerMOS transistor
Logic level FET
120 ^PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅P_D/P_{D 25 ˚C} = f(T_mb)
ID%
120
Normalised Current Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
Fig.2. Normalised continuous drain current.
ID% = 100⋅I_D/I_{D 25 ˚C} = f(T_mb); conditions: V_GS ≥ 5 V
ID, Drain current (Amps)
100
PHP2N20E
10
RDS(ON) ^{= VDS/ID}
tp = 10 us
100 us
1
1 ms
DC
10 ms
100 ms
0.1
1
10
100
VDS, Drain-source voltage (Volts)
1000
Fig.3. Safe operating area. T_mb = 25 ˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
Product specification
PHP3N20L
Zth j-mb, Transient Thermal Impedance (K/W)
10
0.5
1
0.2
0.1
0.05
0.1 _0.02
0
P_D
tp
D
=
tp
T
0.01
T
t
1us 10us 100us 1ms 10ms 0.1s 1s 10s
tp, pulse widtht (s)
Fig.4. Transient thermal impedance.
Z_{th j-mb} = f(t); parameter D = t_p/T
ID, Drain current (Amps)
8
7
Tj = 25 C
6
5 V ^{10 V}
PHP2N20L
4V
3.5 V
5
3V
4
3
2
VGS = 2.5 V
1
0
0
5
10
15
20
25
30
VDS, Drain-Source voltage (Volts)
Fig.5. Typical output characteristics.
I_D = f(V_DS); parameter V_GS
RDS(on), Drain-Source on resistance (Ohms)
PHP2N20L
4
2.5 V
3V
3.5 V 4 V
3
5V
2
VGS = 10 V
1
Tj = 25 C
0
0
1
2
3
4
5
6
7
8
ID, Drain current (Amps)
Fig.6. Typical on-state resistance.
R_DS(ON) = f(I_D); parameter V_GS
September 1997
3
Rev 1.000