PCA9541 Datasheet, PDF (5/30 Pages) NXP Semiconductors – 2-to-1 I2C master selector with interrupt logic and reset

Philips Semiconductors
2-to-1 I²C master selector with interrupt logic and reset
Product data sheet
PCA9541
DEVICE ADDRESS
Following a START condition, the upstream master that wants to
control the I²C-bus or make a status check must send the address
of the slave it is accessing. The slave address of the PCA9541 is
shown in Figure 4. To conserve power, no internal pull-up resistors
are incorporated on the hardware selectable pins and they must be
pulled HIGH or LOW.
1 1 1 A3 A2 A1 A0 R/W
FIXED
HARDWARE
SELECTABLE
SW02011
Figure 4. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1 a read is selected while logic 0
selects a write operation.
COMMAND CODE
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9541, which will be stored
in the Command Code register.
0 0 0 AI 0 0 B1 B0
AUTO
INCREMENT
REGISTER
NUMBER
Figure 5. Command Code
PCA9541 INTERNAL REGISTER MAP
SW02302
The 2 LSBS are used as a pointer to determine which register will
be accessed.
If the auto-increment flag is set (AI=1), the two least significant bits
of the Command Code are automatically incremented after a byte
has been read or written. This allows the user to program the
registers sequentially or to read them sequentially.
– During a Read operation, the contents of these bits will rollover
to “00” after the last allowed register is accessed (“10”).
– During a Write operation, the PCA9541 will acknowledge bytes
sent to the IE and CONTROL registers but will not acknowledge
a byte sent to the Interrupt Status Register since it is a
read-only register. The 2 LSB’s of the Command Code do not
roll over to 00 but stays at 10.
Only the 2 least significant bits are affected by the AI flag.
Unused bits must be programmed with zeroes. Any command code
(Write operation) different from “000AI0000”, “000AI0001”, and
“000AI0010” will not be acknowledged. At power-up, this register
defaults to all zeros.
Table 1. Command Code Register
B1
B0
REGISTER
NAME
TYPE
REGISTER
FUNCTION
0
0
IE
Read/Write
Interrupt
Enable
0
1
CONTROL
Read/Write Control Switch
1
0
ISTAT
Read
Interrupt
Status
1
1
NOT ALLOWED
Each system master controls its own set of registers, however they
can also read specific bits from the other system master.
IE
CONTROL
ISTAT
REG#00
REG#01
REG#10
MASTER 0
SCL_MST0
SDA_MST0
IE 0
CONTROL 0
ISTAT 0
IE 1
CONTROL 1
ISTAT 1
PCA9541
CONTROL 0
REG#00
REG#01
REG#10
IE
CONTROL
ISTAT
MASTER 1
SCL_MST1
SDA_MST1
CONTROL 1
7 6 5 43 2 1 0
CONTROL REGISTER DETAIL
Figure 6. Internal register map
SW02072
2004 Oct 01
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