BUK565-200A Datasheet, PDF (5/7 Pages) NXP Semiconductors – PowerMOS transistor Logic level FET

Philips Semiconductors
PowerMOS transistor
Logic level FET
12 ^{VGS / V}
10
BUK555-200
VDS / V =40
8
160
6
4
2
0
0
20
40
QG / nC
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G); conditions: I_D = 14 A; parameter V_DS
IF / A
30
BUK555-200A
20
Tj / C = 150
25
10
0
0
1
2
VSDS / V
Fig.14. Typical reverse diode current.
I_F = f(V_SDS); conditions: V_GS = 0 V; parameter T_j
Product specification
BUK565-200A
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140 160 180
Tmb / C
Fig.15. Normalised avalanche energy rating.
W_DSS% = f(T_mb); conditions: I_D = 14 A
VGS
0
RGS
L
VDS
T.U.T.
+ ^VDD
-
-ID/100
R 01
shunt
Fig.16. Avalanche energy test circuit.
W_DSS = 0.5 ⋅ LI_D² ⋅ BV_DSS/(BV_DSS − V_DD)
February 1996
5
Rev 1.000