BUK543-60A Datasheet, PDF (5/8 Pages) NXP Semiconductors – PowerMOS transistor Logic level FET

Philips Semiconductors
PowerMOS transistor
Logic level FET
ID / A
1E-01
SUB-THRESHOLD CONDUCTION
1E-02
1E-03
2%
typ
98 %
1E-04
1E-05
1E-06
0
0.4
0.8
1.2
1.6
2
2.4
VGS / V
Fig.11. Sub-threshold drain current.
I_D = f(V_GS); conditions: T_j = 25 ˚C; V_DS = V_GS
C / pF
10000
BUK5y3-50
1000
100
Ciss
Coss
Crss
10
0
20
40
VDS / V
Fig.12. Typical capacitances, C_iss, C_oss, C_rss.
C = f(V_DS); conditions: V_GS = 0 V; f = 1 MHz
VGS / V
12
BUK553-60
10
VDS / V = 12
8
48
6
4
2
0
0 2 4 6 8 10 12 14 16 18 20
QG / nC
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G); conditions: I_D = 20 A; parameter V_DS
Product Specification
BUK543-60A/B
IF / A
50
BUK553-50A
40
30
20
Tj / C = 150
25
10
0
0
1
2
VSDS / V
Fig.14. Typical reverse diode current.
I_F = f(V_SDS); conditions: V_GS = 0 V; parameter T_j
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
20
40
60
80 100 120 140
Ths / C
Fig.15. Normalised avalanche energy rating.
W_DSS% = f(T_hs); conditions: I_D = 20 A
VGS
0
RGS
L
VDS
T.U.T.
+ ^VDD
-
-ID/100
R 01
shunt
Fig.16. Avalanche energy test circuit.
W_DSS = 0.5 ⋅ LI_D² ⋅ BV_DSS/(BV_DSS − V_DD)
April 1993
5
Rev 1.100