74HC_HCT573_15 Datasheet, PDF (5/21 Pages) NXP Semiconductors – Octal D-type transparent latch; 3-state

NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
6. Functional description
Table 3. Function table^[1]
Operating mode
Control
OE
LE
Enable and read register (transparent
L
H
mode)
Latch and read register
L
L
Latch register and disable outputs
H
L
Input
Dn
L
H
l
h
l
h
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
7. Limiting values
Internal
latches
L
H
L
H
L
H
Output
Qn
L
H
L
H
Z
Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
V_CC
I_IK
I_OK
I_O
I_CC
I_GND
T_stg
P_tot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
V_I < 0.5 V or V_I > V_CC + 0.5 V
V_O < 0.5 V or V_O > V_CC + 0.5 V
V_O = 0.5 V to (V_CC + 0.5 V)
DIP20 package
SO20, SSOP20, TSSOP20 and
DHVQFN20 packages
0.5
-
-
-
-
-
65
[1] _-
[2] _-
+7
V
20 mA
20 mA
35 mA
+70 mA
70 mA
+150 C
750 mW
500 mW
[1] For DIP20 package: P_tot derates linearly with 12 mW/K above 70 C.
[2] For SO20: P_tot derates linearly with 8 mW/K above 70 C.
For SSOP20 and TSSOP20 packages: P_tot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN20 package: P_tot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT573
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 26 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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