SAF7113H Datasheet, PDF (48/80 Pages) NXP Semiconductors – 9-bit video input processor

Philips Semiconductors
9-bit video input processor
Product specification
SAF7113H
S
SLAVE ADDRESS W
ACK-s
Sr
SLAVE ADDRESS R
ACK-s
SUBADDRESS
DATA
ACK-s
ACK-m P
data transferred
(n bytes + acknowledge)
MHB340
Fig.34 Read procedure (combined format).
Table 22 Description of I²C-bus format; note 1
CODE
S
Sr
Slave address W
Slave address R
ACK-s
ACK-m
Subaddress
Data
P
X = LSB slave
address
Subaddresses
DESCRIPTION
START condition
repeated START condition
0100 1010 (= 4AH, default) or 0100 1000 (= 48H, if pin RTS0 strapped to ground via a 3.3 kΩ
resistor)
0100 1011 (= 4BH, default) or 0100 1001 (= 49H, if pin RTS0 strapped to ground via a 3.3 kΩ
resistor)
acknowledge generated by the slave
acknowledge generated by the master
subaddress byte; see Table 24
data byte; see Table 24; note 2
STOP condition
read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read
(the circuit is slave transmitter)
00H chip version
read only
01H to 05H front-end part
read and write
06H to 13H decoder part
read and write
14H reserved
−
15H to 17H decoder part
18H to 1EH reserved
1FH video decoder status byte
read and write
−
read only
20H to 3FH reserved
−
40H to 5EH general purpose data slicer
read and write
5FH reserved
−
60H to 62H general purpose data slicer status read only
63H to FFH reserved
−
Notes
1. The SAF7113H supports the ‘fast mode’ I²C-bus specification extension (data rate up to 400 kbits/s).
2. If more than one byte DATA is transmitted the subaddress pointer is automatically incremented.
2000 May 08
48