SAF7113H Datasheet, PDF (24/80 Pages) NXP Semiconductors – 9-bit video input processor

Philips Semiconductors
9-bit video input processor
Product specification
SAF7113H
Table 2 Power-on control sequence
INTERNAL POWER-ON
CONTROL SEQUENCE
PIN OUTPUT STATUS
REMARKS
Directly after power-on
asynchronous reset
VPO7 to VPO0, RTCO, RTS0, RTS1,
direct switching to high-impedance for
SDA and LLC are in high-impedance state 20 to 200 ms
Synchronous reset
sequence
LLC and SDA become active;
internal reset sequence
VPO7 to VPO0, RTCO, RTS0 and RTS1 are
held in high-impedance state
Status after power-on
control sequence
VPO7 to VPO0, RTCO, RTS0 and RTS1 are after power-on (reset sequence) a complete
held in high-impedance state
I²C-bus transmission is required
8.8 Multi-standard VBI data slicer
The multi-standard data slicer is a Vertical Blanking
Interval (VBI) and Full Field (FF) video data acquisition
block. In combination with software modules the slicer
acquires most existing formats of broadcast VBI and FF
data.
The implementation and programming model of the
multi-standard VBI data slicer is similar to the text slicer
built in the “Multimedia Video Data Acquisition Circuit
SAA5284”.
The circuitry recovers the actual clock phase during the
clock-run-in-period, slices the data bits with the selected
data rate, and groups them into bytes. The clock
frequency, signals source, field frequency and accepted
error count must be defined via the I²C-bus in
subaddress 40H, AC1: bits D7 to D4.
Several standards can be selected per VBI line.
The supported VBI data standards are described in
Table 3.
The programming of the desired standards is done via
I²C-bus subaddresses 41H to 57H
(LCR2[7 : 0] to LCR24[7 : 0]); see detailed description in
Chapter 8.10. To adjust the slicers processing to the
signals source, there are offsets in horizontal and vertical
direction available via the I²C-bus in subaddresses 5BH
(bits 2 to 0), 59H (HOFF10 to HOFF0) and 5BH (bit 4),
5AH (VOFF8 to VOFF0). The formatting of the decoded
VBI data is done within the output interface to the
VPO-bus. For a detailed description of the sliced data
format see Table 17.
Table 3 Supported VBI standards
STANDARD TYPE
Teletext EuroWST, CCST
European closed caption
VPS
Wide screen signalling bits
US teletext (WST)
US closed caption (line 21)
Teletext
VITC/EBU time codes (Europe)
VITC/SMPTE time codes (USA)
US NABTS
MOJI (Japanese)
Japanese format switch (L20/22)
DATA RATE
(Mbits/s)
6.9375
0.500
5
5
5.7272
0.503
6.9375
1.8125
1.7898
5.7272
5.7272
5
FRAMING CODE
27H
001
9951H
1E3C1FH
27H
001
programmable
programmable
programmable
programmable
programmable (A7H)
programmable
FC
WINDOW
WST625
CC625
VPS
WSS
WST525
CC525
general text
VITC625
VITC625
NABTS
Japtext
HAM
CHECK
always
always
optional
optional
2000 May 08
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