ISP1582 Datasheet, PDF (48/66 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus peripheral controller

Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Table 66: Interrupt register: bit description…continued
Bit
Symbol
Description
20
EP5RX
Logic 1 indicates the endpoint 5 RX buffer as interrupt source.
19
EP4TX
Logic 1 indicates the endpoint 4 TX buffer as interrupt source.
18
EP4RX
Logic 1 indicates the endpoint 4 RX buffer as interrupt source.
17
EP3TX
Logic 1 indicates the endpoint 3 TX buffer as interrupt source.
16
EP3RX
Logic 1 indicates the endpoint 3 RX buffer as interrupt source.
15
EP2TX
Logic 1 indicates the endpoint 2 TX buffer as interrupt source.
14
EP2RX
Logic 1 indicates the endpoint 2 RX buffer as interrupt source.
13
EP1TX
Logic 1 indicates the endpoint 1 TX buffer as interrupt source.
12
EP1RX
Logic 1 indicates the endpoint 1 RX buffer as interrupt source.
11
EP0TX
Logic 1 indicates the endpoint 0 data TX buffer as interrupt source.
10
EP0RX
Logic 1 indicates the endpoint 0 data RX buffer as interrupt source.
9
-
reserved
8
EP0SETUP Logic 1 indicates that a SETUP token was received on endpoint 0.
7
VBUS
Logic 1 indicates V_BUS is turned on.
6
DMA
DMA status: Logic 1 indicates a change in the DMA Status
register.
5
HS_STAT High speed status: Logic 1 indicates a change from full-speed to
high-speed mode (HS connection). This bit is not set, when the
system goes into full-speed suspend.
4
RESUME Resume status: Logic 1 indicates that a status change from
suspend to resume (active) was detected.
3
SUSP
Suspend status: Logic 1 indicates that a status change from
active to suspend was detected on the bus.
2
PSOF
Pseudo SOF interrupt: Logic 1 indicates that a pseudo SOF or
µSOF was received. Pseudo SOF is an internally generated clock
signal (full-speed: 1 ms period, high-speed: 125 µs period)
synchronized to the USB bus SOF or µSOF.
1
SOF
SOF interrupt: Logic 1 indicates that a SOF or µSOF was
received.
0
BRESET
Bus reset: Logic 1 indicates that a USB bus reset was detected.
When bit OTG in the OTG register is set, BRESET will not be set,
instead, this interrupt bit will report SE0 on DP and DM for 2 ms.
9.5.2 Chip ID register (address: 70h)
This read-only register contains the chip identification and the hardware version
numbers. The firmware should check this information to determine the functions and
features supported. The register contains 3 bytes, and the bit allocation is shown in
Table 67.
Table 67: Chip ID register: bit allocation
Bit
23
22
21
20
19
18
17
16
Symbol
CHIPID[15:8]
Reset
0
0
0
1
0
1
0
1
Bus reset
0
0
0
1
0
1
0
1
Access
R
R
R
R
R
R
R
R
9397 750 13699
Preliminary data
Rev. 03 — 25 August 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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