ISP1582 Datasheet, PDF (12/66 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus peripheral controller

Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
8.6.3 HS detection
The ISP1582 handles more than one electrical state—full-speed (FS) or high-speed
(HS)—under the USB specification. When the USB cable is connected from the
peripheral to the host controller, the ISP1582 defaults to the FS state until it sees a
bus reset from the host controller.
During the bus reset, the peripheral initiates an HS chirp to detect whether the host
controller supports Hi-Speed USB or Original USB. Chirping must be done with the
pull-up resistor connected and the internal termination resistors disabled. If the HS
handshake shows that there is an HS host connected, then the ISP1582 switches to
the HS state.
In the HS state, the ISP1582 should observe the bus for periodic activity. If the bus
remains inactive for 3 ms, the peripheral switches to the FS state to check for a
Single-Ended Zero (SE0) condition on the USB bus. If an SE0 condition is detected
for the designated time (100 µs to 875 µs; refer to section 7.1.7.6 of the USB
specification Rev. 2.0), the ISP1582 switches to the HS chirp state to perform an HS
detection handshake. Otherwise, the ISP1582 remains in the FS state adhering to the
bus-suspend specification.
8.7 Philips Serial Interface Engine (SIE)
The Philips SIE implements the full USB protocol layer. It is completely hardwired for
speed and needs no firmware intervention. The functions of this block include:
synchronization pattern recognition, parallel or serial conversion, bit (de)stuffing,
CRC checking or generation, Packet IDentifier (PID) verification or generation,
address recognition, handshake evaluation or generation.
8.8 SoftConnect
The connection to the USB is established by pulling pin DP (for full-speed devices)
HIGH through a 1.5 kΩ pull-up resistor. In the ISP1582, an external 1.5 kΩ pull-up
resistor must be connected between pin RPU and 3.3 V. Pin RPU connects the
pull-up resistor to pin DP, when bit SOFTCT in the Mode register is set (see Table 20
and Table 21). After a hardware reset, the pull-up resistor is disconnected by default
(bit SOFTCT = 0). The USB bus reset does not change the value of bit SOFTCT.
When the V_BUS is not present, the SOFTCT bit must be set to logic 0 to comply with
the back-drive voltage.
8.9 System controller
The system controller implements the USB power-down capabilities of the ISP1582.
Registers are protected against data corruption during wake-up following a resume
(from the suspend state) by locking the write access until an unlock code has been
written in the Unlock Device register (see Table 73 and Table 74).
8.10 Output pins status
Table 3 illustrates the behavior of output pins when V_CC(I/O) is supplied with V_CC in
various operating conditions.
9397 750 13699
Preliminary data
Rev. 03 — 25 August 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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