UDA1352TS Datasheet, PDF (44/52 Pages) NXP Semiconductors – 48 kHz IEC 60958 audio DAC

Philips Semiconductors
48 kHz IEC 60958 audio DAC
Preliminary specification
UDA1352TS
SYMBOL
PARAMETER
t_SU;DAT
t_HD;DAT
t_SP
data set-up time
data hold time
pulse width of spikes to be suppressed by
the input filter
C_b
capacitive load for each bus line
Note
1. C_b is the total capacity of one bus line.
CONDITIONS MIN.
100
0
0
TYP.
−
−
−
MAX.
−
−
50
UNIT
ns
µs
ns
−
400
pF
handbook, full pagewidth
L3MODE
L3CLOCK
L3DATA
th(L3)A
tsu(L3)A
tCLK(L3)L
tCLK(L3)H
tsu(L3)DA
BIT 0
th(L3)DA
tsu(L3)A
th(L3)A
Tcy(CLK)(L3)
BIT 7
MGL723
Fig.15 Timing for address mode.
2002 Nov 22
44