UDA1352TS Datasheet, PDF (25/52 Pages) NXP Semiconductors – 48 kHz IEC 60958 audio DAC

Philips Semiconductors
48 kHz IEC 60958 audio DAC
Preliminary specification
UDA1352TS
12.1 SPDIF mute setting (write)
Table 19 Register address 01H
BIT
Symbol
Default
15
14
13
12
11
10
−
−
−
−
−
−
−
−
−
−
−
−
9
8
−
MUTEBP
−
0
BIT
Symbol
Default
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
Table 20 Description of register bits
BIT
15 to 9
8
7 to 3
2 to 0
SYMBOL
−
MUTEBP
−
−
DESCRIPTION
reserved
Mute bypass setting. A 1-bit value to disable the mute bypass setting. When this mute
bypass setting is enabled, then even in out-of-lock situations or non-PCM data detected,
the output data will not be suppressed. If this bit is logic 0, then the output will be muted in
out-of-lock situations. If this bit is logic 1, then the output will not be muted in out-of-lock
situations. Default value 0.
reserved
When writing new settings via the L3-bus or I²C-bus interface, these bits should always
remain at logic 0 (default value) to guarantee correct operation.
2002 Nov 22
25