P89V51RD2 Datasheet, PDF (42/75 Pages) NXP Semiconductors – 8-bit 80C51 5 V low power 64 kB Flash microcontroller with 1 kB RAM

Philips Semiconductors
P89V51RD2
8-bit microcontrollers with 80C51 core
SCK Cycle #
(for reference)
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(from Master)
MISO
(from Slave)
SS (to Slave)
1
2
3
4
5
6
7
8
MSB 6
5
4
3
2
1 LSB
MSB
6
5
4
3
2
1 LSB
Fig 17. SPI transfer format with CPHA = 0.
002aaa529
SCK Cycle #
(for reference)
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(from Master)
MISO
(from Slave)
SS (to Slave)
1
2
3
4
5
6
7
8
MSB 6
5
4
3
2
1 LSB
MSB 6
5
4
3
2
1
LSB
002aaa530
Fig 18. SPI transfer format with CPHA = 1.
7.7 Watchdog timer
The device offers a programmable Watchdog Timer (WDT) for fail safe protection
against software deadlock and automatic recovery.
To protect the system against software deadlock, the user software must refresh the
WDT within a user-defined time period. If the software fails to do this periodical
refresh, an internal hardware reset will be initiated if enabled (WDRE = 1). The
software can be designed such that the WDT times out if the program does not work
properly.
The WDT in the device uses the system clock (XTAL1) as its time base. So strictly
speaking, it is a Watchdog counter rather than a Watchdog timer. The WDT register
will increment every 344,064 crystal clocks. The upper 8-bits of the time base register
(WDTD) are used as the reload register of the WDT.
The WDTS flag bit is set by WDT overflow and is not changed by WDT reset. User
software can clear WDTS by writing ‘1' to it.
Figure 19 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD)
control Watchdog timer operation. During idle mode, WDT operation is temporarily
suspended, and resumes upon an interrupt exit from idle.
The time-out period of the WDT is calculated as follows:
9397 750 12964
Product data
Rev. 01 — 01 March 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
42 of 75