ISP1181A Datasheet, PDF (40/70 Pages) NXP Semiconductors – Full-speed Universal Serial Bus peripheral controller

Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Bit
7
6
5
4
3
2
1
0
Symbol
CHIPIDL[7:0]
Reset
41H
Access
R
R
R
R
R
R
R
R
Table 47: Chip ID Register: bit description
Bit
Symbol
Description
15 to 8 CHIPIDH[7:0] chip ID code (81H)
7 to 0
CHIPIDL[7:0] silicon version (41H, with 41H representing the BCD encoded
version number)
12.3.6 Read Interrupt Register
This command indicates the sources of interrupts as stored in the 4-byte Interrupt
Register. Each individual endpoint has its own interrupt bit. The bit allocation of the
Interrupt Register is shown in Table 48. Bit BUSTATUS is used to verify the current
bus status in the interrupt service routine. Interrupts are enabled via the Interrupt
Enable Register, see Section 12.1.5.
While reading the interrupt register, read all the 4 bytes completely.
Code (Hex): C0 — read interrupt register
Transaction — read 4 bytes
Table 48: Interrupt Register: bit allocation
Bit
31
30
29
Symbol
Reset
0
0
0
Access
R
R
R
Bit
23
22
21
Symbol
EP14
EP13
EP12
Reset
0
0
0
Access
R
R
R
Bit
15
14
13
Symbol
EP6
EP5
EP4
Reset
0
0
0
Access
R
R
R
Bit
7
6
5
Symbol BUSTATUS reserved
PSOF
Reset
0
0
0
Access
R
R
R
28
27
reserved
0
0
R
R
20
19
EP11
EP10
0
0
R
R
12
11
EP3
EP2
0
0
R
R
4
3
SOF
EOT
0
0
R
R
26
25
24
0
R
18
EP9
0
R
10
EP1
0
R
2
SUSPND
0
R
0
R
17
EP8
0
R
9
EP0IN
0
R
1
RESUME
0
R
0
R
16
EP7
0
R
8
EP0OUT
0
R
0
RESET
0
R
9397 750 13959
Product data
Table 49:
Bit
31 to 24
23 to 10
9
Interrupt Register: bit description
Symbol
Description
-
reserved
EP14 to EP1 A logic 1 indicates the interrupt source(s): endpoint 14 to 1.
EP0IN
A logic 1 indicates the interrupt source: control IN endpoint.
Rev. 05 — 08 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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