ISP1181A Datasheet, PDF (28/70 Pages) NXP Semiconductors – Full-speed Universal Serial Bus peripheral controller

Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
12.1.4 Write/Read Hardware Configuration
This command is used to access the Hardware Configuration Register, which
consists of 2 bytes. The first (lower) byte contains the device configuration and
control values, the second (upper) byte holds the clock control bits and the clock
division factor. The bit allocation is given in Table 20. A bus reset will not change any
of the programmed bit values.
The Hardware Configuration Register controls the connection to the USB bus, clock
activity and power supply during ‘suspend’ state, output clock frequency, DMA
operating mode and pin configurations (polarity, signalling mode).
Code (Hex): BA/BB — write/read Hardware Configuration Register
Transaction — write/read 2 bytes
Table 20: Hardware Configuration Register: bit allocation
Bit
15
14
13
12
Symbol
reserved EXTPUL NOLAZY CLKRUN
Reset
0
0
1
0
Access
R/W
R/W
R/W
R/W
Bit
7
6
5
4
Symbol
DAKOLY DRQPOL DAKPOL EOTPOL
Reset
0
1
0
0
Access
R/W
R/W
R/W
R/W
11
0
R/W
3
WKUPCS
0
R/W
10
9
CLKDIV[3:0]
0
1
R/W
R/W
2
1
PWROFF INTLVL
0
0
R/W
R/W
8
1
R/W
0
INTPOL
0
R/W
9397 750 13959
Product data
Table 21: Hardware Configuration Register: bit description
Bit
Symbol
Description
15
-
reserved
14
EXTPUL
A logic 1 indicates that an external 1.5 kΩ pull-up resistor is
used on pin D+ and that SoftConnect is not used. Bus reset
value: unchanged.
13
NOLAZY
A logic 1 disables output on pin CLKOUT of the LazyClock
frequency (100 kHz ± 50 %) during ‘suspend’ state. A logic 0
causes pin CLKOUT to switch to LazyClock output after
approximately 2 ms delay, following the setting of bit GOSUSP
in the Mode Register. Bus reset value: unchanged.
12
CLKRUN
A logic 1 indicates that the internal clocks are always running,
even during ‘suspend’ state. A logic 0 switches off the internal
oscillator and PLL, when they are not needed. During ‘suspend’
state this bit must be made logic 0 to meet the suspend current
requirements. The clock is stopped after a delay of
approximately 2 ms, following the setting of bit GOSUSP in the
Mode Register. Bus reset value: unchanged.
11 to 8
CLKDIV[3:0]
This field specifies the clock division factor N, which controls the
clock frequency on output CLKOUT. The output frequency in
MHz is given by 48 ⁄ (N + 1) . The clock frequency range is
3 MHz to 48 MHz (N = 0 to 15). with a reset value of 12 MHz
(N = 3). The hardware design guarantees no glitches during
frequency change. Bus reset value: unchanged.
7
DAKOLY
A logic 1 selects DACK-only DMA mode. A logic 0 selects 8237
compatible DMA mode. Bus reset value: unchanged.
Rev. 05 — 08 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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