PHT6N03T Datasheet, PDF (4/10 Pages) NXP Semiconductors – TrenchMOS transistor Standard level FET

Philips Semiconductors
TrenchMOS™ transistor
Standard level FET
Product specification
PHT6N03T
120 ^PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅P_D/P_{D 25 ˚C} = f(T_mb)
ID%
120
110
100
90
Normalised Current Derating
80
70
60
50
40
30
20
10
0
0
20 40 60 80 100 120 140
Tmb / C
Fig.2. Normalised continuous drain current.
ID% = 100⋅I_D/I_{D 25 ˚C} = f(T_mb); conditions: V_GS ≥ 10 V
ID / A
100
10
RDS(ON) ^{= VDS / ID}
1
DC
0.1
7830-30
tp = 10 us
100 us
1 ms
10 ms
100 ms
0.01
0.1
1
10
100
1000
VDS / V
Fig.3. Safe operating area. T_mb = 25 ˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
Zth j-amb / (K/W)
1E+02
D=
0.5
BUKX83
1E+01 ^0.2
0.1
0.05
0.02
1E+00
P
D
t_p
D = ^tp
T
1E-01
0
1E-02
1E-07
1E-05
1E-03 1E-01
t/s
t
T
1E+01 1E+03
Fig.4. Transient thermal impedance.
Z_{th j-mb} = f(t); parameter D = t_p/T
ID / A
60
12 10
50
BUK7830-30
8
VGS / V =
40
6.5
30
6
20
5.5
10
5
4.5
4
0
0
2
4
6
8
10
VDS / V
Fig.5. Typical output characteristics, T_j = 25 ˚C.
I_D = f(V_DS); parameter V_GS
RDS(ON) / mOhm
6
6
6.5
5
7830-30
8
4
10
3
12
2
VGS / V =
1
0
0
10
20
30
40
50
60
ID / A
Fig.6. Typical on-state resistance, T_j = 25 ˚C.
R_DS(ON) = f(I_D); parameter V_GS
November 1997
4
Rev 1.200