PHT6N03T Datasheet, PDF (1/10 Pages) NXP Semiconductors – TrenchMOS transistor Standard level FET

Philips Semiconductors
TrenchMOS™ transistor
Standard level FET
Product specification
PHT6N03T
GENERAL DESCRIPTION
N-channel enhancement mode
standard level field-effect power
transistor in a plastic envelope
suitable for surface mounting. Using
’trench’ technology, the device
features very low on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended for use in DC-DC
converters and general purpose
switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
T_j
R_DS(ON)
Drain-source voltage
Drain current (DC) T_sp = 25 ˚C
Drain current (DC) T_amb = 25 ˚C
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V_GS = 10 V
PINNING - SOT223
PIN
DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
PIN CONFIGURATION
4
1
2
3
SYMBOL
g
MAX.
30
12.8
5.9
8.3
150
30
d
s
UNIT
V
A
A
W
˚C
mΩ
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DS
V_DGR
±V_GS
I_D
I_D
I_DM
P_tot
T_stg, T_j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
-
R_GS = 20 kΩ
-
T_sp = 25 ˚C
T_amb = 25 ˚C
T_sp = 100 ˚C
T_amb = 100 ˚C
T_sp = 25 ˚C
T_amb = 25 ˚C
T_sp = 25 ˚C
T_amb = 25 ˚C
-
THERMAL RESISTANCES
SYMBOL
R_{th j-sp}
R_{th j-amb}
PARAMETER
Thermal resistance junction to
solder point
Thermal resistance junction to
ambient
CONDITIONS
Mounted on any PCB
Mounted on PCB of Fig.19
MIN.
-
-
-
-
-
-
-
-
-
-
-
- 55
TYP.
12
-
MAX.
30
30
16
12.8
5.9
9
4.1
51.2
23.6
8.3
1.8
150
MAX.
15
70
UNIT
V
V
V
A
A
A
A
A
A
W
W
˚C
UNIT
K/W
K/W
November 1997
1
Rev 1.200