PHP60N06LT Datasheet, PDF (4/9 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP60N06LT, PHB60N06LT
1000
ID/A
100
RDS(ON) =VDS/ID
tp =
1 us
10us
DC
10
100 us
1 ms
10ms
100ms
1
1
10
VDS/V
100
Fig.3. Safe operating area. T_mb = 25 ˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
10 ^Zth/(K/W)
1
0.5
0.2
0.1
0.1 _0.05
0.02
0.01 0
P_D
tp
D
=
tp
T
T
t
0.001
1E-06
0.0001
0.01
1
100
t/s
Fig.4. Transient thermal impedance.
Z_{th j-mb} = f(t); parameter D = t_p/T
100 ₁₀
ID/A 5
4.4
80
VGS/V =
4.2
4.0
3.8
60
3.6
3.4
40
3.2
3.0
20
2.8
2.6
2.4
0
2.2
0
2
4 _VDS/V 6
8
10 2.0
Fig.5. Typical output characteristics, T_j = 25 ˚C.
I_D = f(V_DS); parameter V_GS
24 ^RDS(ON)/mOhm
23
22
VGS/V =
21
20
19
4
4.2
4.4
4.6
4.8
5
18
17
16
15
14
13 ₀
10 20 30 40 _ID/A50 60 70 80 90
Fig.6. Typical on-state resistance, T_j = 25 ˚C.
R_DS(ON) = f(I_D); parameter V_GS
100
ID/A
80
60
40
20
Tj/C =
175
25
0
0
1
2
3 _VGS/V 4
5
6
Fig.7. Typical transfer characteristics.
I_D = f(V_GS) ; conditions: V_DS = 25 V; parameter T_j
50
gfs/S
40
30
20
10
0
0
20
40 _ID/A 60
80
100
Fig.8. Typical transconductance, T_j = 25 ˚C.
g_fs = f(I_D); conditions: V_DS = 25 V
January 1998
4
Rev 1.300